From 34fce0e34da5a88bd7ae732482c082cf1dc29cd9 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Tue, 23 Jan 2024 13:47:22 -0800
Subject: [PATCH] Commented out TLRAMCoalescerFuzzer test module

---
 src/main/resources/vsrc/SimMemFuzzer.v        |  2 +-
 .../scala/radiance/memory/Coalescing.scala    | 32 +++++++++++++++++++
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/src/main/resources/vsrc/SimMemFuzzer.v b/src/main/resources/vsrc/SimMemFuzzer.v
index 0114b2f..263eb24 100644
--- a/src/main/resources/vsrc/SimMemFuzzer.v
+++ b/src/main/resources/vsrc/SimMemFuzzer.v
@@ -120,7 +120,7 @@ module SimMemFuzzer #(parameter NUM_LANES = 4) (
         __in_finished
       );
       for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
-        $display("verilog: %04d valid[%d]=%d, address[%d]=%d, __in_d_ready[%d]=%d",
+        $display("verilog: %04d a_valid[%d]=%d, a_address[%d]=0x%x, d_ready[%d]=%d",
           $time, tid, __in_a_valid[tid], tid, __in_a_address[tid], tid, __in_d_ready[tid]);
       end
 
diff --git a/src/main/scala/radiance/memory/Coalescing.scala b/src/main/scala/radiance/memory/Coalescing.scala
index 4bcab30..e1e5cdb 100644
--- a/src/main/scala/radiance/memory/Coalescing.scala
+++ b/src/main/scala/radiance/memory/Coalescing.scala
@@ -2426,6 +2426,38 @@ class TLRAMCoalescerLoggerTest(filename: String, timeout: Int = 500000)(implicit
   io.finished := dut.io.finished
 }
 
+// // fuzzer --> coalescer --> tlram
+// class TLRAMCoalescerFuzzer(implicit p: Parameters) extends LazyModule {
+//   val numLanes = p(SIMTCoreKey).get.nLanes
+//   val config = DefaultCoalescerConfig.copy(numLanes = numLanes)
+
+//   val coal = LazyModule(new CoalescingUnit(config))
+//   val driver = LazyModule(new MemTraceDriver(config))
+//   val rams = Seq.fill(numLanes + 1)( // +1 for coalesced edge
+//     LazyModule(
+//       // NOTE: beatBytes here sets the data bitwidth of the upstream TileLink
+//       // edges globally, by way of Diplomacy communicating the TL slave
+//       // parameters to the upstream nodes.
+//       new TLRAM(
+//         address = AddressSet(0x0000, 0xffffff),
+//         beatBytes = (1 << config.dataBusWidth)
+//       )
+//     )
+//   )
+
+//   class Impl extends LazyModuleImp(this) with UnitTestModule {
+//     // io.start is unused since MemTraceDriver doesn't accept io.start
+//     io.finished := driver.module.io.finished
+//   }
+// }
+
+// class TLRAMCoalescerFuzzerTest(timeout: Int = 500000)(implicit p: Parameters)
+//     extends UnitTest(timeout) {
+//   val dut = Module(LazyModule(new TLRAMCoalescerFuzzer).module)
+//   dut.io.start := io.start
+//   io.finished := dut.io.finished
+// }
+
 // tracedriver --> coalescer --> tlram
 class TLRAMCoalescer(implicit p: Parameters) extends LazyModule {
   val numLanes = p(SIMTCoreKey).get.nLanes