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Remove leftover printf

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This commit is contained in:
Hansung Kim
2023-04-17 21:17:23 -07:00
parent 02ce969c67
commit 334d05b222
1 changed files with 6 additions and 7 deletions
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13
src/main/scala/tilelink/Coalescing.scala
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@@ -824,7 +824,6 @@ class MemTraceLogger(
req.size := tlIn.a.bits.size req.size := tlIn.a.bits.size
req.is_store := tlAOpcodeIsStore(tlIn.a.bits.opcode) req.is_store := tlAOpcodeIsStore(tlIn.a.bits.opcode)
req.source := tlIn.a.bits.source req.source := tlIn.a.bits.source
printf("======== req.source=%d\n", req.source)
// TL always carries the exact unaligned address that the client // TL always carries the exact unaligned address that the client
// originally requested, so no postprocessing required // originally requested, so no postprocessing required
req.address := tlIn.a.bits.address req.address := tlIn.a.bits.address
@@ -864,7 +863,6 @@ class MemTraceLogger(
resp.size := tlOut.d.bits.size resp.size := tlOut.d.bits.size
resp.is_store := tlDOpcodeIsStore(tlOut.d.bits.opcode) resp.is_store := tlDOpcodeIsStore(tlOut.d.bits.opcode)
resp.source := tlOut.d.bits.source resp.source := tlOut.d.bits.source
printf("======== resp.source=%d\n", resp.source)
// NOTE: TL D channel doesn't carry address nor mask, so there's no easy // NOTE: TL D channel doesn't carry address nor mask, so there's no easy
// way to figure out which bytes the master actually use. Since we // way to figure out which bytes the master actually use. Since we
// don't care too much about addresses in the trace anyway, just store // don't care too much about addresses in the trace anyway, just store
@@ -874,7 +872,8 @@ class MemTraceLogger(
} }
// Flatten per-lane signals to the Verilog blackbox input. // Flatten per-lane signals to the Verilog blackbox input.
// clunky workaround of the fact that Chisel doesn't allow partial //
// This is a clunky workaround of the fact that Chisel doesn't allow partial
// assignment to a bitfield range of a wide signal. // assignment to a bitfield range of a wide signal.
def flattenTrace(traceLogIO: Bundle with HasTraceLine, perLane: Vec[TraceLine]) = { def flattenTrace(traceLogIO: Bundle with HasTraceLine, perLane: Vec[TraceLine]) = {
// these will get optimized out // these will get optimized out
@@ -908,10 +907,10 @@ class MemTraceLogger(
} }
} }
// MemTraceLogger is bidirectional. The DPI module tells itself if it's logging // MemTraceLogger is bidirectional, and `isResponse` is how the DPI module tells
// the request stream or the response stream by `isResponse`. This distinction // itself whether it's logging the request stream or the response stream. This
// is needed because the response trace file will not contain certain columns // is necessary because we have to generate slightly different trace format
// such as address. // depending on this, e.g. response trace will not contain an address column.
class SimMemTraceLogger(isResponse: Boolean, filename: String, numLanes: Int) class SimMemTraceLogger(isResponse: Boolean, filename: String, numLanes: Int)
extends BlackBox( extends BlackBox(
Map( Map(