Fix fp exception by rounding right after MulRawFN
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Hansung Kim
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@@ -25,7 +25,7 @@ class TensorDotProductUnit(val half: Boolean) extends Module with tile.HasFPUPar
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val in = Flipped(Valid(new Bundle {
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val a = Vec(dotProductDim, Bits((inFLen).W))
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val b = Vec(dotProductDim, Bits((inFLen).W))
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val c = Bits((inFLen).W)
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val c = Bits((outFLen).W) // note C has the out length for accumulation
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}))
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val stall = Input(Bool())
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val out = Valid(new Bundle {
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@@ -39,7 +39,7 @@ class TensorDotProductUnit(val half: Boolean) extends Module with tile.HasFPUPar
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val tag = if (half) H else S
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val in1 = io.in.bits.a.map(x => unbox(recode(x, tag), tag, Some(tIn)))
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val in2 = io.in.bits.b.map(x => unbox(recode(x, tag), tag, Some(tIn)))
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val in3 = unbox(recode(io.in.bits.c, tag), tag, Some(tIn))
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val in3 = unbox(recode(io.in.bits.c, S), S, Some(tOut))
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val dpu = Module(new DotProductPipe(dotProductDim, tIn, tOut))
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dpu.io.in.valid := io.in.valid
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@@ -111,7 +111,7 @@ class DotProductPipe(dim: Int, inputType: tile.FType, outputType: tile.FType) ex
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val in = Flipped(Valid(new Bundle {
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val a = Vec(4, Bits((recInFLen).W))
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val b = Vec(4, Bits((recInFLen).W))
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val c = Bits((recInFLen).W)
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val c = Bits((recOutFLen).W)
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// val roundingMode = UInt(3.W)
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// val detectTininess = UInt(1.W)
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}))
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@@ -121,55 +121,54 @@ class DotProductPipe(dim: Int, inputType: tile.FType, outputType: tile.FType) ex
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})
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})
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val rawZero = hardfloat.rawFloatFromRecFN(expWidth, sigWidth, 0.U(recInFLen.W))
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val mul = Seq.fill(dim)(Module(new hardfloat.MulFullRawFN(expWidth, sigWidth)))
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val mulOuts = mul.zipWithIndex.map { case (m, i) =>
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// FIXME: these settings are arbitrary
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// m.io.roundingMode := hardfloat.consts.round_near_even
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// m.io.detectTininess := hardfloat.consts.tininess_afterRounding
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// m.io.a := io.in.bits.a(i)
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// m.io.b := io.in.bits.b(i)
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val rawInA = hardfloat.rawFloatFromRecFN(expWidth, sigWidth, io.in.bits.a(i))
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val rawInB = hardfloat.rawFloatFromRecFN(expWidth, sigWidth, io.in.bits.b(i))
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m.io.a := rawInA
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m.io.b := rawInB
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// m.io.invalidExc output ignored
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// assert(rawInA.isNaN === false.B)
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// assert(rawInA.isInf === false.B)
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// assert(rawInB.isNaN === false.B)
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// assert(rawInB.isInf === false.B)
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// tie down to zero when invalid
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val rawInAOr0 = Mux(io.in.valid, rawInA, rawZero)
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val rawInBOr0 = Mux(io.in.valid, rawInB, rawZero)
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m.io.a := rawInAOr0
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m.io.b := rawInBOr0
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// assert(m.io.invalidExc === false.B)
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// round fp16*fp16 raw result back to fp32 recoded format
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val mulExpWidth = m.io.rawOut.expWidth
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val mulSigWidth = m.io.rawOut.sigWidth
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val roundRawFNToRecFN =
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Module(new hardfloat.RoundAnyRawFNToRecFN(
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mulExpWidth, mulSigWidth, outExpWidth, outSigWidth, 0))
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roundRawFNToRecFN.io.invalidExc := m.io.invalidExc
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roundRawFNToRecFN.io.infiniteExc := false.B
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roundRawFNToRecFN.io.in := m.io.rawOut
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roundRawFNToRecFN.io.roundingMode := hardfloat.consts.round_near_even
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roundRawFNToRecFN.io.detectTininess := hardfloat.consts.tininess_afterRounding
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// assert(roundRawFNToRecFN.io.exceptionFlags === 0.U)
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roundRawFNToRecFN.io.out
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}
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val mulStageOut = StallingPipe(io.stall, io.in.valid, VecInit(mul.map(_.io.rawOut)))
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val mulStageOut = StallingPipe(io.stall, io.in.valid, VecInit(mulOuts))
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val mulStageC = StallingPipe(io.stall, io.in.valid, io.in.bits.c)
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val mulExpWidth = mulStageOut.bits.head.expWidth
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val mulSigWidth = mulStageOut.bits.head.sigWidth
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// mul stage end -------------------------------------------------------------
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val add1 = Seq.fill(dim / 2)(Module(new hardfloat.AddRawFN(mulExpWidth, mulSigWidth)))
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val add1 = Seq.fill(dim / 2)(Module(new hardfloat.AddRecFN(outExpWidth, outSigWidth)))
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val add1Outs = add1.zipWithIndex.map { case (a, i) =>
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a.io.subOp := 0.U // FIXME dont know what this is
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a.io.a := mulStageOut.bits(2 * i + 0)
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a.io.b := mulStageOut.bits(2 * i + 1)
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a.io.roundingMode := hardfloat.consts.round_near_even
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// a.io.detectTininess := hardfloat.consts.tininess_afterRounding
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// a.io.invalidExc output ignored
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// assert(a.io.invalidExc === false.B)
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// round back to fp32 recoded format
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// FIXME: awkward to do this in the middle; do right after mul?
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val addExpWidth = a.io.rawOut.expWidth
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val addSigWidth = a.io.rawOut.sigWidth
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val roundRawFNToRecFN =
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Module(new hardfloat.RoundAnyRawFNToRecFN(addExpWidth, addSigWidth, outExpWidth, outSigWidth, 0))
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roundRawFNToRecFN.io.invalidExc := a.io.invalidExc
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roundRawFNToRecFN.io.infiniteExc := false.B
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roundRawFNToRecFN.io.in := a.io.rawOut
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roundRawFNToRecFN.io.roundingMode := hardfloat.consts.round_near_even
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roundRawFNToRecFN.io.detectTininess := hardfloat.consts.tininess_afterRounding
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roundRawFNToRecFN.io.out
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// roundRawFNToRecFN.io.exceptionFlags ignored
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a.io.detectTininess := hardfloat.consts.tininess_afterRounding
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// assert(a.io.exceptionFlags === 0.U)
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a.io.out
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}
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// val add1StageOut = StallingPipe(io.stall, mulStageOut.valid, VecInit(add1.map(_.io.out)))
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val add1StageOut = StallingPipe(io.stall, mulStageOut.valid, VecInit(add1Outs))
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val add1StageC = StallingPipe(io.stall, mulStageOut.valid, mulStageC.bits)
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@@ -177,35 +176,25 @@ class DotProductPipe(dim: Int, inputType: tile.FType, outputType: tile.FType) ex
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val add2 = Module(new hardfloat.AddRecFN(outExpWidth, outSigWidth))
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add2.io.subOp := 0.U // FIXME
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assert(add1StageOut.bits.length == 2)
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add2.io.a := add1StageOut.bits(0)
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add2.io.b := add1StageOut.bits(1)
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add2.io.roundingMode := hardfloat.consts.round_near_even
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add2.io.detectTininess := hardfloat.consts.tininess_afterRounding
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assert(add2.io.exceptionFlags === 0.U)
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// assert(add2.io.exceptionFlags === 0.U)
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val add2StageOut = StallingPipe(io.stall, add1StageOut.valid, add2.io.out)
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val add2StageC = StallingPipe(io.stall, add1StageOut.valid, add1StageC.bits)
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// add2 stage end ------------------------------------------------------------
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// convert to recoded format for addition to C
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// TODO: raw+raw addition might be cheaper?
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val recToRec = Module(
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new hardfloat.RecFNToRecFN(expWidth, sigWidth, outExpWidth, outSigWidth))
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recToRec.io.in := add2StageC.bits
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recToRec.io.roundingMode := hardfloat.consts.round_near_even
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recToRec.io.detectTininess := hardfloat.consts.tininess_afterRounding
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assert(recToRec.io.exceptionFlags === 0.U)
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val add2StageCRec = recToRec.io.out
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val acc = Module(new hardfloat.AddRecFN(outExpWidth, outSigWidth))
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acc.io.subOp := 0.U // FIXME
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acc.io.a := add2StageOut.bits
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acc.io.b := add2StageCRec
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// acc.io.b := add2StageCRec
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acc.io.b := add2StageC.bits
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acc.io.roundingMode := hardfloat.consts.round_near_even
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acc.io.detectTininess := hardfloat.consts.tininess_afterRounding
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assert(acc.io.exceptionFlags === 0.U)
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// assert(acc.io.exceptionFlags === 0.U)
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val accStageOut = StallingPipe(io.stall, add2StageOut.valid, acc.io.out)
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