Fix CoalShiftQueue invalidate logic
IO type change to Valid[UInt] was not reflected in the valid bit logic.
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@@ -13,6 +13,7 @@ import freechips.rocketchip.unittest._
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trait InFlightTableSizeEnum extends ChiselEnum {
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trait InFlightTableSizeEnum extends ChiselEnum {
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val INVALID: Type
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val INVALID: Type
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val FOUR: Type
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def logSizeToEnum(x: UInt): Type
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def logSizeToEnum(x: UInt): Type
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def enumToLogSize(x: Type): UInt
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def enumToLogSize(x: Type): UInt
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}
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}
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@@ -184,7 +185,7 @@ class CoalShiftQueue[T <: Data](
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if (i == -1) true.B else if (i == entries) false.B else mask(i)
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if (i == -1) true.B else if (i == entries) false.B else mask(i)
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}
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}
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def paddedUsed = pad({ i: Int => used(i) })
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def paddedUsed = pad({ i: Int => used(i) })
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def validAfterInv(i: Int) = valid(i) && !io.invalidate.bits(i)
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def validAfterInv(i: Int) = valid(i) && (!io.invalidate.valid || !io.invalidate.bits(i))
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val shift = (used =/= 0.U) && (io.queue.deq.ready || !validAfterInv(0))
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val shift = (used =/= 0.U) && (io.queue.deq.ready || !validAfterInv(0))
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for (i <- 0 until entries) {
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for (i <- 0 until entries) {
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@@ -26,7 +26,7 @@ class MultiPortQueueUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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for (_ <- 0 until 100) {
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for (_ <- 0 until 100) {
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c.clock.step()
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c.clock.step()
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}
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}
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// c.io.deq(0).valid.expect(false.B)
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// c.io.deq(0).valid.expect(false.B)
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}
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}
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}
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}
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}
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}
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@@ -186,7 +186,7 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
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}
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}
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it should "dequeue invalidated entries by itself" in {
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it should "dequeue invalidated entries by itself" in {
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test(new CoalShiftQueue(UInt(8.W), 4)) { c =>
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test(new CoalShiftQueue(gen = UInt(8.W), entries = 4)) { c =>
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c.io.invalidate.valid.poke(false.B)
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c.io.invalidate.valid.poke(false.B)
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// prepare
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// prepare
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@@ -195,12 +195,10 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
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c.io.queue.enq.valid.poke(true.B)
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c.io.queue.enq.valid.poke(true.B)
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c.io.queue.enq.bits.poke(0x12.U)
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c.io.queue.enq.bits.poke(0x12.U)
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c.clock.step()
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c.clock.step()
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c.io.queue.deq.ready.poke(false.B)
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c.io.queue.enq.ready.expect(true.B)
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c.io.queue.enq.ready.expect(true.B)
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c.io.queue.enq.valid.poke(true.B)
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c.io.queue.enq.valid.poke(true.B)
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c.io.queue.enq.bits.poke(0x34.U)
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c.io.queue.enq.bits.poke(0x34.U)
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c.clock.step()
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c.clock.step()
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c.io.queue.deq.ready.poke(false.B)
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c.io.queue.enq.ready.expect(true.B)
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c.io.queue.enq.ready.expect(true.B)
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c.io.queue.enq.valid.poke(true.B)
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c.io.queue.enq.valid.poke(true.B)
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c.io.queue.enq.bits.poke(0x56.U)
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c.io.queue.enq.bits.poke(0x56.U)
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@@ -210,12 +208,13 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
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// invalidate two entries at head
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// invalidate two entries at head
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c.io.invalidate.valid.poke(true.B)
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c.io.invalidate.valid.poke(true.B)
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c.io.invalidate.bits.poke(0x3.U)
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c.io.invalidate.bits.poke(0x3.U)
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// [ 0x56 | 0x34(inv) | 0x12(inv) ]
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c.clock.step()
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c.clock.step()
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// 0x12 should have been dequeued now
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// [ 0x56 | 0x34(inv) ]
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c.io.invalidate.valid.poke(false.B)
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c.io.invalidate.valid.poke(false.B)
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c.io.queue.deq.ready.poke(false.B)
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c.io.queue.deq.ready.poke(false.B)
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c.clock.step()
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c.clock.step()
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// 0x34 should have been dequeued now
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// [ 0x56 ]
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c.io.queue.deq.ready.poke(true.B)
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c.io.queue.deq.ready.poke(true.B)
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c.io.queue.deq.valid.expect(true.B)
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c.io.queue.deq.valid.expect(true.B)
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c.io.queue.deq.bits.expect(0x56.U)
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c.io.queue.deq.bits.expect(0x56.U)
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@@ -254,21 +253,22 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
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}
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}
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}
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}
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object testConfig extends CoalescerConfig(
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object testConfig
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MAX_SIZE = 4, // maximum coalesced size
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extends CoalescerConfig(
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DEPTH = 2, // request window per lane
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MAX_SIZE = 4, // maximum coalesced size
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WAIT_TIMEOUT = 8, // max cycles to wait before forced fifo dequeue, per lane
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DEPTH = 2, // request window per lane
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ADDR_WIDTH = 24, // assume <= 32
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WAIT_TIMEOUT = 8, // max cycles to wait before forced fifo dequeue, per lane
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DATA_BUS_SIZE = 4, // 2^4=16 bytes, 128 bit bus
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ADDR_WIDTH = 24, // assume <= 32
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NUM_LANES = 4,
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DATA_BUS_SIZE = 4, // 2^4=16 bytes, 128 bit bus
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// WATERMARK = 2, // minimum buffer occupancy to start coalescing
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NUM_LANES = 4,
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WORD_SIZE = 4, // 32-bit system
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// WATERMARK = 2, // minimum buffer occupancy to start coalescing
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WORD_WIDTH = 2, // log(WORD_SIZE)
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WORD_SIZE = 4, // 32-bit system
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NUM_OLD_IDS = 16, // num of outstanding requests per lane, from processor
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WORD_WIDTH = 2, // log(WORD_SIZE)
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NUM_NEW_IDS = 4, // num of outstanding coalesced requests
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NUM_OLD_IDS = 16, // num of outstanding requests per lane, from processor
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COAL_SIZES = Seq(3),
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NUM_NEW_IDS = 4, // num of outstanding coalesced requests
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SizeEnum = DefaultInFlightTableSizeEnum
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COAL_SIZES = Seq(3),
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)
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SizeEnum = DefaultInFlightTableSizeEnum
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)
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class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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behavior of "uncoalescer"
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behavior of "uncoalescer"
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@@ -351,7 +351,13 @@ class CoalInflightTableUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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val sizeBits = 2
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val sizeBits = 2
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val inflightCoalReqTableEntry =
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val inflightCoalReqTableEntry =
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new InflightCoalReqTableEntry(numLanes, numPerLaneReqs, sourceWidth, offsetBits, testConfig.SizeEnum)
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new InflightCoalReqTableEntry(
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numLanes,
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numPerLaneReqs,
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sourceWidth,
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offsetBits,
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testConfig.SizeEnum
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)
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// it should "stop enqueueing when full" in {
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// it should "stop enqueueing when full" in {
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// test(new InflightCoalReqTable(numLanes, sourceWidth, entries)) { c =>
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// test(new InflightCoalReqTable(numLanes, sourceWidth, entries)) { c =>
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