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tensor: Fix writeback datawidth

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This commit is contained in:
Hansung Kim
2024-10-15 15:45:59 -07:00
parent ab8d3554bb
commit 2ca2ee37b0
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/radiance/core/TensorCoreDecoupled.scala
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@@ -42,7 +42,7 @@ class TensorCoreDecoupled(
val writeback = Decoupled(new Bundle { val writeback = Decoupled(new Bundle {
val last = Bool() val last = Bool()
val wid = UInt(numWarpBits.W) val wid = UInt(numWarpBits.W)
val data = Vec(numLanes, UInt(wordSize.W)) val data = Vec(numLanes, UInt((wordSize * 8/*bits*/).W))
}) })
val respA = Flipped(Decoupled(new TensorMemResp(sourceWidth, dataWidth))) val respA = Flipped(Decoupled(new TensorMemResp(sourceWidth, dataWidth)))
val respB = Flipped(Decoupled(new TensorMemResp(sourceWidth, dataWidth))) val respB = Flipped(Decoupled(new TensorMemResp(sourceWidth, dataWidth)))
@@ -135,7 +135,7 @@ class TensorCoreDecoupled(
// Execute stage // Execute stage
// ------------- // -------------
// Execute backend of the decoupled access/execute pipeline. // Backend of the decoupled access/execute pipeline.
// //
val respQueueDepth = 4 // FIXME: parameterize val respQueueDepth = 4 // FIXME: parameterize
val respQueueA = Queue(io.respA, respQueueDepth) val respQueueA = Queue(io.respA, respQueueDepth)
@@ -144,7 +144,7 @@ class TensorCoreDecoupled(
respQueueB.ready := io.writeback.ready // FIXME respQueueB.ready := io.writeback.ready // FIXME
require(respQueueA.bits.data.widthOption.get == require(respQueueA.bits.data.widthOption.get ==
io.writeback.bits.data.widthOption.get * numLanes, io.writeback.bits.data.widthOption.get,
"response data width does not match the writeback data width") "response data width does not match the writeback data width")
// FIXME: debug dummy: pipe A directly to writeback // FIXME: debug dummy: pipe A directly to writeback