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Fix TL data mask stencil logic in MemTraceLogger

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This commit is contained in:
Hansung Kim
2023-04-23 00:39:59 -07:00
parent 6cd27faed2
commit 2a82e8d119
1 changed files with 6 additions and 1 deletions
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7
src/main/scala/tilelink/Coalescing.scala
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@@ -181,6 +181,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModule
resp.isStore := TLUtils.DOpcodeIsStore(tlOut.d.bits.opcode) resp.isStore := TLUtils.DOpcodeIsStore(tlOut.d.bits.opcode)
resp.size := tlOut.d.bits.size resp.size := tlOut.d.bits.size
resp.data := tlOut.d.bits.data resp.data := tlOut.d.bits.data
// NOTE: D channel doesn't have mask
// Queue up responses that didn't get coalesced originally ("noncoalesced" responses). // Queue up responses that didn't get coalesced originally ("noncoalesced" responses).
// Coalesced (but uncoalesced back) responses will also be enqueued into the same queue. // Coalesced (but uncoalesced back) responses will also be enqueued into the same queue.
@@ -954,8 +955,12 @@ class MemTraceLogger(
"mask HIGH bits do not match the TL size. This should have been handled by the TL generator logic" "mask HIGH bits do not match the TL size. This should have been handled by the TL generator logic"
) )
val trailingZerosInMask = trailingZeros(tlIn.a.bits.mask) val trailingZerosInMask = trailingZeros(tlIn.a.bits.mask)
val mask = ~((~0.U) << (trailingZerosInMask * 8.U)) val dataW = tlIn.params.dataBits
val mask = ~(~(0.U(dataW.W)) << ((1.U << tlIn.a.bits.size) * 8.U))
req.data := mask & (tlIn.a.bits.data >> (trailingZerosInMask * 8.U)) req.data := mask & (tlIn.a.bits.data >> (trailingZerosInMask * 8.U))
// when (req.valid) {
// printf("trailingZerosInMask=%d, mask=%x, data=%x\n", trailingZerosInMask, mask, req.data)
// }
when(req.valid) { when(req.valid) {
TracePrintf( TracePrintf(