From 257232dec8b93595f96d84a78cf93e258cea5804 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Fri, 10 Nov 2023 15:04:32 -0800
Subject: [PATCH] Require MSHR size matches nSrcId to L2

---
 src/main/scala/rocket/VortexFatBank.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/rocket/VortexFatBank.scala b/src/main/scala/rocket/VortexFatBank.scala
index ad0c5c3..238a138 100644
--- a/src/main/scala/rocket/VortexFatBank.scala
+++ b/src/main/scala/rocket/VortexFatBank.scala
@@ -25,6 +25,8 @@ case class L1SystemConfig(
   def coreTagPlusSizeWidth: Int = {
     log2Ceil(wordSize) + coreTagWidth
   }
+  require(mshrSize == l2ReqSourceGenSize,
+    "MSHR size must match the number of sourceIds to downstream.")
 }
 
 object defaultL1SystemConfig
@@ -38,9 +40,7 @@ object defaultL1SystemConfig
       l2ReqSourceGenSize = 8,
       uncachedAddrSets = Seq(AddressSet(0x2000000L, 0xffL)),
       icacheInstAddrSets = Seq(AddressSet(0x80000000L, 0xfffffffL))
-    ) {
-  require(mshrSize != l2ReqSourceGenSize)
-}
+    )
 
 class L1System(config: L1SystemConfig)(implicit p: Parameters)
     extends LazyModule {