Separate read and write counter for smem

This commit is contained in:
Hansung Kim
2024-07-02 14:52:58 -07:00
parent 7aad800a2d
commit 21baeae758

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@@ -483,13 +483,20 @@ class RadianceClusterModuleImp(outer: RadianceCluster) extends ClusterModuleImp(
// read OR write access counter for smem banks // read OR write access counter for smem banks
val smem_bank_mgrs_grouped = outer.smem_bank_mgrs.grouped(outer.smem_subbanks) val smem_bank_mgrs_grouped = outer.smem_bank_mgrs.grouped(outer.smem_subbanks)
val numBanks = smem_bank_mgrs_grouped.length val numBanks = smem_bank_mgrs_grouped.length
val smemCounterPerBankPerCycle = Seq.fill(numBanks)(Seq.fill(outer.smem_subbanks) val counterWidth = 32
(Wire(UInt(32.W)))) val smemReadsPerBankPerCycle = Seq.fill(numBanks)(Seq.fill(outer.smem_subbanks)
val smemCounterPerCycle = smemCounterPerBankPerCycle.map(_.reduce(_ + _)).reduce(_ + _) (Wire(UInt(counterWidth.W))))
val smemCounter = RegInit(UInt(32.W), 0.U) val smemWritesPerBankPerCycle = Seq.fill(numBanks)(Seq.fill(outer.smem_subbanks)
smemCounter := smemCounter + smemCounterPerCycle (Wire(UInt(counterWidth.W))))
smemCounterPerBankPerCycle.foreach(_.foreach(dontTouch(_))) val smemReadsPerCycle = smemReadsPerBankPerCycle.map(_.reduce(_ + _)).reduce(_ + _)
dontTouch(smemCounter) val smemWritesPerCycle = smemWritesPerBankPerCycle.map(_.reduce(_ + _)).reduce(_ + _)
val smemReadCounter = RegInit(UInt(counterWidth.W), 0.U)
val smemWriteCounter = RegInit(UInt(counterWidth.W), 0.U)
smemReadCounter := smemReadCounter + smemReadsPerCycle
smemWriteCounter := smemWriteCounter + smemWritesPerCycle
// smemReadsPerBankPerCycle.foreach(_.foreach(dontTouch(_)))
dontTouch(smemReadCounter)
dontTouch(smemWriteCounter)
if (outer.stride_by_word) { if (outer.stride_by_word) {
outer.smem_bank_mgrs.grouped(outer.smem_subbanks).zipWithIndex.foreach { case (bank_mgrs, bid) => outer.smem_bank_mgrs.grouped(outer.smem_subbanks).zipWithIndex.foreach { case (bank_mgrs, bid) =>
@@ -526,7 +533,8 @@ class RadianceClusterModuleImp(outer: RadianceCluster) extends ClusterModuleImp(
make_buffer(mem, r_node, r_edge, w_node, w_edge) make_buffer(mem, r_node, r_edge, w_node, w_edge)
// add access counters to banks // add access counters to banks
smemCounterPerBankPerCycle(bid)(wid) := (r_node.a.fire === true.B) +& (w_node.a.fire === true.B) smemReadsPerBankPerCycle(bid)(wid) := (r_node.a.fire === true.B)
smemWritesPerBankPerCycle(bid)(wid) := (w_node.a.fire === true.B)
} }
} }
} else { } else {