From 218e3cad921e17923e4356eaa0ecdc160454da91 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Sat, 22 Jul 2023 16:27:47 -0700 Subject: [PATCH] Rename TracerSystemMem -> CanHaveMemtraceCore --- .../{TracerSystemMem.scala => CanHaveMemtraceCore.scala} | 1 + 1 file changed, 1 insertion(+) rename src/main/scala/tilelink/{TracerSystemMem.scala => CanHaveMemtraceCore.scala} (97%) diff --git a/src/main/scala/tilelink/TracerSystemMem.scala b/src/main/scala/tilelink/CanHaveMemtraceCore.scala similarity index 97% rename from src/main/scala/tilelink/TracerSystemMem.scala rename to src/main/scala/tilelink/CanHaveMemtraceCore.scala index 56bd43e..0bcbd70 100644 --- a/src/main/scala/tilelink/TracerSystemMem.scala +++ b/src/main/scala/tilelink/CanHaveMemtraceCore.scala @@ -5,6 +5,7 @@ import freechips.rocketchip.subsystem.BaseSubsystem import org.chipsalliance.cde.config.Parameters // TODO: possibly move to somewhere closer to CoalescingUnit +// TODO: separate coalescer config from CanHaveMemtraceCore // The trait is attached to DigitalTop of Chipyard system, informing it indeed // has the ability to attach GPU tracer node onto the system bus