From 215ac369cbe39c0f65369eacda1517af589630fb Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Sat, 23 Mar 2024 13:48:44 -0700 Subject: [PATCH] Do proper barrier param negotiation for numCores --- src/main/scala/radiance/tile/Barrier.scala | 48 ++++++++++++------- .../scala/radiance/tile/RadianceCluster.scala | 1 + .../scala/radiance/tile/RadianceTile.scala | 21 +------- src/main/scala/radiance/tile/VortexCore.scala | 10 ++-- 4 files changed, 38 insertions(+), 42 deletions(-) diff --git a/src/main/scala/radiance/tile/Barrier.scala b/src/main/scala/radiance/tile/Barrier.scala index 25adafe..269a62c 100644 --- a/src/main/scala/radiance/tile/Barrier.scala +++ b/src/main/scala/radiance/tile/Barrier.scala @@ -14,12 +14,12 @@ import freechips.rocketchip.diplomacy._ case class EmptyParams() case class BarrierParams( - barrierIdBits: Int, - numCoreBits: Int + barrierIdBits: Int, + numCoreBits: Int ) class BarrierRequestBits( - param: BarrierParams + param: BarrierParams ) extends Bundle { val barrierId = UInt(param.barrierIdBits.W) val sizeMinusOne = UInt(param.numCoreBits.W) @@ -27,7 +27,7 @@ class BarrierRequestBits( } class BarrierResponseBits( - param: BarrierParams + param: BarrierParams ) extends Bundle { val barrierId = UInt(param.barrierIdBits.W) } @@ -38,28 +38,38 @@ class BarrierBundle(param: BarrierParams) extends Bundle { } // FIXME Separate BarrierEdgeParams from BarrierParams -object BarrierNodeImp extends SimpleNodeImp[BarrierParams, EmptyParams, BarrierParams, BarrierBundle] { - def edge(pd: BarrierParams, pu: EmptyParams, p: Parameters, sourceInfo: SourceInfo) = { - // barrier parameters flow strictly downward from the master node - pd +object BarrierNodeImp extends SimpleNodeImp[BarrierParams, BarrierParams, BarrierParams, BarrierBundle] { + def edge(pd: BarrierParams, pu: BarrierParams, p: Parameters, sourceInfo: SourceInfo) = { + println(s"==== BarrierNodeImp: barrierIdBits=${pd.barrierIdBits}, numCoreBits=${pu.numCoreBits}") + require(pd.barrierIdBits >= 0 && pu.numCoreBits >= 0) + BarrierParams(barrierIdBits = pd.barrierIdBits, numCoreBits = pu.numCoreBits) } def bundle(e: BarrierParams) = new BarrierBundle(e) // FIXME render def render(e: BarrierParams) = RenderedEdge(colour = "ffffff", label = "X") } -case class BarrierMasterNode(val srcParams: BarrierParams)(implicit valName: ValName) - extends SourceNode(BarrierNodeImp)(Seq(srcParams)) -case class BarrierSlaveNode(val numEdges: Int)(implicit valName: ValName) - extends SinkNode(BarrierNodeImp)(Seq.fill(numEdges)(EmptyParams())) +case class BarrierMasterNode(val barrierIdBits: Int)(implicit valName: ValName) + extends SourceNode(BarrierNodeImp)({ + require(barrierIdBits >= 0) + Seq(BarrierParams(barrierIdBits = barrierIdBits, numCoreBits = -1 /* unset */)) + }) +case class BarrierSlaveNode(val numCores: Int)(implicit valName: ValName) + extends SinkNode(BarrierNodeImp)({ + require(numCores > 0) + val numCoreBits = log2Ceil(numCores) + Seq.fill(numCores)( + BarrierParams(barrierIdBits = -1 /* unset */, numCoreBits = numCoreBits) + ) + }) // `delay`: number of cycles used to delay the response after all cores are // synchronized. This is used for debugging purposes to give some time for the // cores to "settle" after the barrier synchronization, e.g. resolve // outstanding smem requests. class BarrierSynchronizer( - param: BarrierParams, - delay: Option[Int] = None + param: BarrierParams, + delay: Option[Int] = None ) extends Module { val numBarriers = 1 << param.barrierIdBits val numCores = 1 << param.numCoreBits @@ -71,13 +81,15 @@ class BarrierSynchronizer( }) // 2-dimensional table of per-id, per-core "done" signals - val table = RegInit(VecInit(Seq.fill(numBarriers)(VecInit(Seq.fill(numCores)(false.B))))) + val table = RegInit( + VecInit(Seq.fill(numBarriers)(VecInit(Seq.fill(numCores)(false.B)))) + ) val done = Seq.fill(numBarriers)(Wire(Bool())) val delayer = delay.map(n => Seq.fill(numBarriers)(Counter(n))) (table zip done).zipWithIndex.foreach { case ((row, d), i) => d := row.reduce(_ && _) - delayer.foreach{ dl => when (d) { dl(i).inc() }} + delayer.foreach { dl => when(d) { dl(i).inc() } } dontTouch(d) } @@ -86,7 +98,7 @@ class BarrierSynchronizer( req.ready := true.B when(req.fire) { assert(coreId.U === req.bits.coreId) - // FIXME: don't need coreId to be hardware here + // @cleanup: coreId don't need to be hardware table(req.bits.barrierId)(coreId.U) := true.B } } @@ -95,7 +107,7 @@ class BarrierSynchronizer( (doneArbiter.io.in zip done).zipWithIndex.foreach { case ((in, d), i) => val alarm = delayer match { case Some(dl) => dl(i).value === (dl(i).n - 1).U - case None => true.B + case None => true.B } in.valid := (d && alarm) in.bits := d diff --git a/src/main/scala/radiance/tile/RadianceCluster.scala b/src/main/scala/radiance/tile/RadianceCluster.scala index f45607f..01584d3 100644 --- a/src/main/scala/radiance/tile/RadianceCluster.scala +++ b/src/main/scala/radiance/tile/RadianceCluster.scala @@ -102,6 +102,7 @@ class RadianceClusterModuleImp(outer: RadianceCluster) extends ClusterModuleImp( // cores are configured to have the same barrier id range. While true, might // be better to actually assert this val barrierParam = outer.barrierSlaveNode.in(0)._2 + println(s"======= barrierParam: ${barrierParam}") val synchronizer = Module(new BarrierSynchronizer(barrierParam)) (synchronizer.io.reqs zip outer.barrierSlaveNode.in).foreach { case (req, (b, _)) => req <> b.req diff --git a/src/main/scala/radiance/tile/RadianceTile.scala b/src/main/scala/radiance/tile/RadianceTile.scala index 7d323ee..defb3f0 100644 --- a/src/main/scala/radiance/tile/RadianceTile.scala +++ b/src/main/scala/radiance/tile/RadianceTile.scala @@ -329,11 +329,8 @@ class RadianceTile private ( // Barrier synchronization node // FIXME: hardcoded params val numBarriers = 8 - val numCores = 2 def barrierIdBits = log2Ceil(numBarriers) - def coreIdBits = log2Ceil(numCores) - val barrierParams = BarrierParams(barrierIdBits = barrierIdBits, numCoreBits = coreIdBits) - val barrierMasterNode = BarrierMasterNode(barrierParams) + val barrierMasterNode = BarrierMasterNode(barrierIdBits) val base = p(GPUMemory()) match { case Some(GPUMemParams(baseAddr, _)) => baseAddr @@ -786,22 +783,6 @@ class RadianceTileModuleImp(outer: RadianceTile) // } } -class ClusterSynchronizer( - barrierIdWidth: Int, - numCoreWidth: Int, -) extends Module { - val io = IO(new Bundle { - val req = Flipped(Decoupled(new Bundle { - val barrierId = UInt(barrierIdWidth.W) - val sizeMinusOne = UInt(numCoreWidth.W) - val coreId = UInt(numCoreWidth.W) - })) - val resp = Decoupled(new Bundle { - val barrierId = UInt(barrierIdWidth.W) - }) - }) -} - // Some @copypaste from CoalescerSourceGen. class VortexTLAdapter( newSourceWidth: Int, diff --git a/src/main/scala/radiance/tile/VortexCore.scala b/src/main/scala/radiance/tile/VortexCore.scala index b9634aa..ab2e1ef 100644 --- a/src/main/scala/radiance/tile/VortexCore.scala +++ b/src/main/scala/radiance/tile/VortexCore.scala @@ -90,13 +90,15 @@ class VortexBundle(tile: RadianceTile)(implicit p: Parameters) extends CoreBundl val smem_d_ready = Output(UInt((tile.numLsuLanes * 1).W)) // FIXME: hardcoded + val barrierIdBits = tile.barrierMasterNode.out(0)._2.barrierIdBits + val coreIdBits = tile.barrierMasterNode.out(0)._2.numCoreBits val gbar_req_valid = Output(Bool()) - val gbar_req_id = Output(UInt(tile.barrierIdBits.W)) - val gbar_req_size_m1 = Output(UInt(tile.coreIdBits.W)) - val gbar_req_core_id = Output(UInt(tile.coreIdBits.W)) + val gbar_req_id = Output(UInt(barrierIdBits.W)) + val gbar_req_size_m1 = Output(UInt(coreIdBits.W)) + val gbar_req_core_id = Output(UInt(coreIdBits.W)) val gbar_req_ready = Input(Bool()) val gbar_rsp_valid = Input(Bool()) - val gbar_rsp_id = Input(UInt(tile.barrierIdBits.W)) + val gbar_rsp_id = Input(UInt(barrierIdBits.W)) // val fpu = Flipped(new FPUCoreIO()) //val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))