From 2091ef686be304337dd5e2bb04782de3c118376b Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 23 Oct 2023 14:50:15 -0700 Subject: [PATCH] Rename defaultConfig -> DefaultCoalescerConfig --- src/main/scala/tilelink/CanHaveMemtraceCore.scala | 2 +- src/main/scala/tilelink/Coalescing.scala | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/main/scala/tilelink/CanHaveMemtraceCore.scala b/src/main/scala/tilelink/CanHaveMemtraceCore.scala index 0bcbd70..d6dee4d 100644 --- a/src/main/scala/tilelink/CanHaveMemtraceCore.scala +++ b/src/main/scala/tilelink/CanHaveMemtraceCore.scala @@ -15,7 +15,7 @@ trait CanHaveMemtraceCore { this: BaseSubsystem => p(MemtraceCoreKey).map { param => // Safe to use get as WithMemtraceCore requires WithNLanes to be defined val simtParam = p(SIMTCoreKey).get - val config = defaultConfig.copy( + val config = DefaultCoalescerConfig.copy( numLanes = simtParam.nLanes, numOldSrcIds = simtParam.nSrcIds ) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index ead99c0..1b4d71a 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -99,14 +99,14 @@ case class CoalescerConfig( } -object defaultConfig extends CoalescerConfig( +object DefaultCoalescerConfig extends CoalescerConfig( enable = true, numLanes = 4, queueDepth = 1, waitTimeout = 8, addressWidth = 24, - dataBusWidth = 4, // if "4": 2^4=16 bytes, 128 bit bus - coalLogSizes = Seq(4), + dataBusWidth = 4, // if "4": 2^4=16 bytes, 128 bit bus + coalLogSizes = Seq(4), // if "4": 2^4=16 bytes, 128 bit bus // watermark = 2, wordSizeInBytes = 4, // when attaching to SoC, 16 source IDs are not enough due to longer latency @@ -1995,7 +1995,7 @@ class DummyDriverImp(outer: DummyDriver, config: CoalescerConfig) // Should not instantiate any memtrace modules. class DummyCoalescer(implicit p: Parameters) extends LazyModule { val numLanes = p(SIMTCoreKey).get.nLanes - val config = defaultConfig.copy(numLanes = numLanes) + val config = DefaultCoalescerConfig.copy(numLanes = numLanes) val driver = LazyModule(new DummyDriver(config)) val rams = Seq.fill(config.numLanes + 1)( // +1 for coalesced edge @@ -2032,7 +2032,7 @@ class DummyCoalescerTest(timeout: Int = 500000)(implicit p: Parameters) class TLRAMCoalescerLogger(filename: String)(implicit p: Parameters) extends LazyModule { val numLanes = p(SIMTCoreKey).get.nLanes - val config = defaultConfig.copy(numLanes = numLanes) + val config = DefaultCoalescerConfig.copy(numLanes = numLanes) val driver = LazyModule(new MemTraceDriver(config, filename)) val coreSideLogger = LazyModule( @@ -2092,7 +2092,7 @@ class TLRAMCoalescerLoggerTest(filename: String, timeout: Int = 500000)(implicit // tracedriver --> coalescer --> tlram class TLRAMCoalescer(implicit p: Parameters) extends LazyModule { val numLanes = p(SIMTCoreKey).get.nLanes - val config = defaultConfig.copy(numLanes = numLanes) + val config = DefaultCoalescerConfig.copy(numLanes = numLanes) val filename = "vecadd.core1.thread4.trace" val coal = LazyModule(new CoalescingUnit(config))