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Parameterize tracefile has_source from Config

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This commit is contained in:
Hansung Kim
2023-05-09 22:22:27 -07:00
parent 89398cdc3d
commit 1886aefcc1
5 changed files with 32 additions and 31 deletions
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4
src/main/resources/csrc/SimMemTrace.cc
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@@ -152,7 +152,7 @@ MemTraceLine MemTraceReader::read_trace_at(const long cycle, const int lane_id,
assert(!"unreachable"); assert(!"unreachable");
} }
extern "C" void memtrace_init(const char *filename) { extern "C" void memtrace_init(const char *filename, bool has_source) {
#ifndef NO_VPI #ifndef NO_VPI
s_vpi_vlog_info info; s_vpi_vlog_info info;
if (!vpi_get_vlog_info(&info)) { if (!vpi_get_vlog_info(&info)) {
@@ -175,7 +175,7 @@ extern "C" void memtrace_init(const char *filename) {
reader = std::make_unique<MemTraceReader>(filename); reader = std::make_unique<MemTraceReader>(filename);
// parse file upfront // parse file upfront
// driver trace file is assumed to not have source id // driver trace file is assumed to not have source id
reader->parse(false); reader->parse(has_source);
} }
// TODO: accept core_id as well // TODO: accept core_id as well

2
src/main/resources/csrc/SimMemTrace.h
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@@ -44,7 +44,7 @@ public:
FILE *outfile; FILE *outfile;
}; };
extern "C" void memtrace_init(const char *filename); extern "C" void memtrace_init(const char *filename, bool has_source);
extern "C" void memtrace_query(unsigned char trace_read_ready, extern "C" void memtrace_query(unsigned char trace_read_ready,
unsigned long trace_read_cycle, unsigned long trace_read_cycle,
int trace_read_lane_id, int trace_read_lane_id,

9
src/main/resources/vsrc/SimMemTrace.v
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@@ -4,7 +4,8 @@
`define LOGSIZE_WIDTH 8 `define LOGSIZE_WIDTH 8
import "DPI-C" function void memtrace_init( import "DPI-C" function void memtrace_init(
input string filename input string filename,
input bit has_source
); );
// Make sure to sync the parameters for: // Make sure to sync the parameters for:
@@ -24,7 +25,9 @@ import "DPI-C" function void memtrace_query
output bit trace_read_finished output bit trace_read_finished
); );
module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) ( module SimMemTrace #(parameter FILENAME = "undefined",
NUM_LANES = 4,
HAS_SOURCE = 0) (
input clock, input clock,
input reset, input reset,
@@ -61,7 +64,7 @@ module SimMemTrace #(parameter FILENAME = "undefined", NUM_LANES = 4) (
initial begin initial begin
/* $value$plusargs("uartlog=%s", __uartlog); */ /* $value$plusargs("uartlog=%s", __uartlog); */
memtrace_init(FILENAME); memtrace_init(FILENAME, HAS_SOURCE);
end end
always @(posedge clock) begin always @(posedge clock) begin

24
src/main/scala/tilelink/Coalescing.scala
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@@ -13,7 +13,7 @@ import freechips.rocketchip.unittest._
// TODO: find better place for these // TODO: find better place for these
case class SIMTCoreParams(nLanes: Int = 4) case class SIMTCoreParams(nLanes: Int = 4)
case class MemtraceCoreParams(tracefilename: String = "undefined") case class MemtraceCoreParams(tracefilename: String = "undefined", traceHasSource: Boolean = false)
case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None /*default*/) case object SIMTCoreKey extends Field[Option[SIMTCoreParams]](None /*default*/)
case object MemtraceCoreKey extends Field[Option[MemtraceCoreParams]](None /*default*/) case object MemtraceCoreKey extends Field[Option[MemtraceCoreParams]](None /*default*/)
@@ -1062,9 +1062,11 @@ object TLUtils {
} }
} }
class MemTraceDriver(config: CoalescerConfig, filename: String)(implicit // `traceHasSource` is true if the input trace file has an additional source
p: Parameters // ID column. This is useful for using the output trace file genereated by
) extends LazyModule { // MemTraceLogger as the driver.
class MemTraceDriver(config: CoalescerConfig, filename: String, traceHasSource: Boolean = false)
(implicit p: Parameters) extends LazyModule {
// Create N client nodes together // Create N client nodes together
val laneNodes = Seq.tabulate(config.numLanes) { i => val laneNodes = Seq.tabulate(config.numLanes) { i =>
val clientParam = Seq( val clientParam = Seq(
@@ -1082,7 +1084,7 @@ class MemTraceDriver(config: CoalescerConfig, filename: String)(implicit
val node = TLIdentityNode() val node = TLIdentityNode()
laneNodes.foreach { l => node := l } laneNodes.foreach { l => node := l }
lazy val module = new MemTraceDriverImp(this, config, filename) lazy val module = new MemTraceDriverImp(this, config, filename, traceHasSource)
} }
trait HasTraceLine { trait HasTraceLine {
@@ -1105,7 +1107,8 @@ class TraceLine extends Bundle with HasTraceLine {
val data = UInt(64.W) val data = UInt(64.W)
} }
class MemTraceDriverImp(outer: MemTraceDriver, config: CoalescerConfig, filename: String) class MemTraceDriverImp(outer: MemTraceDriver, config: CoalescerConfig, filename: String,
traceHasSource: Boolean)
extends LazyModuleImp(outer) extends LazyModuleImp(outer)
with UnitTestModule { with UnitTestModule {
// Current cycle mark to read from trace // Current cycle mark to read from trace
@@ -1119,7 +1122,7 @@ class MemTraceDriverImp(outer: MemTraceDriver, config: CoalescerConfig, filename
// Are we safe to read the next warp? // Are we safe to read the next warp?
val reqQueueAllReady = reqQueues.map(_.io.enq.ready).reduce(_ && _) val reqQueueAllReady = reqQueues.map(_.io.enq.ready).reduce(_ && _)
val sim = Module(new SimMemTrace(filename, config.numLanes)) val sim = Module(new SimMemTrace(filename, config.numLanes, traceHasSource))
sim.io.clock := clock sim.io.clock := clock
sim.io.reset := reset.asBool sim.io.reset := reset.asBool
// 'sim.io.trace_ready.ready' is a ready signal going into the DPI sim, // 'sim.io.trace_ready.ready' is a ready signal going into the DPI sim,
@@ -1251,10 +1254,11 @@ class MemTraceDriverImp(outer: MemTraceDriver, config: CoalescerConfig, filename
} }
} }
class SimMemTrace(filename: String, numLanes: Int, traceHasSource: Boolean)
class SimMemTrace(filename: String, numLanes: Int)
extends BlackBox( extends BlackBox(
Map("FILENAME" -> filename, "NUM_LANES" -> numLanes) Map("FILENAME" -> filename,
"NUM_LANES" -> numLanes,
"HAS_SOURCE" -> (if (traceHasSource) 1 else 0))
) )
with HasBlackBoxResource { with HasBlackBoxResource {
val traceLineT = new TraceLine val traceLineT = new TraceLine

24
src/main/scala/tilelink/TracerSystemMem.scala
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@@ -1,8 +1,8 @@
package freechips.rocketchip.tilelink package freechips.rocketchip.tilelink
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.subsystem.{BaseSubsystem} import freechips.rocketchip.subsystem.BaseSubsystem
import org.chipsalliance.cde.config.{Parameters, Config} import org.chipsalliance.cde.config.Parameters
// The trait is attached to DigitalTop of Chipyard system, informing it indeed // The trait is attached to DigitalTop of Chipyard system, informing it indeed
// has the ability to attach GPU tracer node onto the system bus // has the ability to attach GPU tracer node onto the system bus
@@ -13,20 +13,14 @@ trait CanHaveMemtraceCore { this: BaseSubsystem =>
// Safe to use get as WithMemtraceCore requires WithNLanes to be defined // Safe to use get as WithMemtraceCore requires WithNLanes to be defined
val simtParam = p(SIMTCoreKey).get val simtParam = p(SIMTCoreKey).get
val config = defaultConfig.copy(numLanes = simtParam.nLanes) val config = defaultConfig.copy(numLanes = simtParam.nLanes)
val tracer = LazyModule(new MemTraceDriver(config, param.tracefilename)(p)) val tracer = LazyModule(
new MemTraceDriver(config, param.tracefilename, param.traceHasSource)(p)
)
// Must use :=* to ensure the N edges from Tracer doesn't get merged into 1 // Must use :=* to ensure the N edges from Tracer doesn't get merged into 1
// when connecting to SBus // when connecting to SBus
println(s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]") println(
s"============ MemTraceDriver instantiated [filename=${param.tracefilename}]"
)
sbus.fromPort(Some("gpu-tracer"))() :=* tracer.node sbus.fromPort(Some("gpu-tracer"))() :=* tracer.node
} }
} }
//This is used by Chip Level Config, the config which creates the SoC
class WithMemtraceCore(tracefilename: String)
extends Config((site, _, _) => { case MemtraceCoreKey =>
require(
site(SIMTCoreKey).isDefined,
"Memtrace core requires a SIMT configuration. Use WithNLanes to enable SIMT."
)
Some(MemtraceCoreParams(tracefilename))
})