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Connect stlNode of Gemmini

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This commit is contained in:
Hansung Kim
2024-01-23 18:58:03 -08:00
parent 2e5f6d8427
commit 17553ccfcd
1 changed files with 8 additions and 3 deletions
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11
src/main/scala/radiance/tile/VortexTile.scala
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@@ -17,6 +17,7 @@ import freechips.rocketchip.prci.ClockSinkParameters
import freechips.rocketchip.regmapper.RegField import freechips.rocketchip.regmapper.RegField
import freechips.rocketchip.tile._ import freechips.rocketchip.tile._
import radiance.memory._ import radiance.memory._
import gemmini.{Gemmini, GemminiCustomConfigs}
case class VortexTileParams( case class VortexTileParams(
core: VortexCoreParams = VortexCoreParams(), core: VortexCoreParams = VortexCoreParams(),
@@ -342,9 +343,13 @@ class VortexTile private (
} }
// ROCC // ROCC
val roccs = p(BuildRoCC).map(_(p)) // TODO: parametrize
roccs.map(_.atlNode).foreach { atl => tlMasterXbar.node :=* atl } val gemmini = LazyModule(new Gemmini(GemminiCustomConfigs.unifiedMemConfig))
roccs.map(_.tlNode).foreach { tl => tlOtherMastersNode :=* tl } val roccs: Seq[LazyRoCC] = Seq(gemmini)
tlMasterXbar.node :=* gemmini.atlNode
tlOtherMastersNode :=* gemmini.tlNode
gemmini.stlNode :=* TLWidthWidget(4) :=* smemXbar.node
/* below are copied from rocket */ /* below are copied from rocket */