diff --git a/src/main/resources/csrc/SimMemFuzzer.cc b/src/main/resources/csrc/SimMemFuzzer.cc
index e8accb3..e0a7799 100644
--- a/src/main/resources/csrc/SimMemFuzzer.cc
+++ b/src/main/resources/csrc/SimMemFuzzer.cc
@@ -5,16 +5,18 @@
 #include <stdio.h>
 #include <stdint.h>
 
+extern "C" void memfuzz_init_rs(int num_lanes);
+
 extern "C" void memfuzz_generate_rs(uint8_t *vec_a_ready, uint8_t *vec_a_valid,
                                     long long *vec_a_address,
                                     uint8_t *vec_a_is_store, int *vec_a_size,
                                     long long *vec_a_data, uint8_t *vec_d_ready,
                                     uint8_t *vec_d_valid,
                                     uint8_t *vec_d_is_store, int *vec_d_size,
-                                    uint8_t *finished);
+                                    uint8_t inflight, uint8_t *finished);
 
 extern "C" void memfuzz_init(int num_lanes) {
-  printf("from C: num_lanes=%d\n", num_lanes);
+  memfuzz_init_rs(num_lanes);
 }
 
 extern "C" void memfuzz_generate(uint8_t *vec_a_ready, uint8_t *vec_a_valid,
@@ -22,8 +24,9 @@ extern "C" void memfuzz_generate(uint8_t *vec_a_ready, uint8_t *vec_a_valid,
                                  uint8_t *vec_a_is_store, int *vec_a_size,
                                  long long *vec_a_data, uint8_t *vec_d_ready,
                                  uint8_t *vec_d_valid, uint8_t *vec_d_is_store,
-                                 int *vec_d_size, uint8_t *finished) {
+                                 int *vec_d_size, uint8_t inflight,
+                                 uint8_t *finished) {
   memfuzz_generate_rs(vec_a_ready, vec_a_valid, vec_a_address, vec_a_is_store,
                       vec_a_size, vec_a_data, vec_d_ready, vec_d_valid,
-                      vec_d_is_store, vec_d_size, finished);
+                      vec_d_is_store, vec_d_size, inflight, finished);
 }
diff --git a/src/main/resources/vsrc/SimMemFuzzer.v b/src/main/resources/vsrc/SimMemFuzzer.v
index d5a6bdb..0114b2f 100644
--- a/src/main/resources/vsrc/SimMemFuzzer.v
+++ b/src/main/resources/vsrc/SimMemFuzzer.v
@@ -22,6 +22,7 @@ import "DPI-C" function void memfuzz_generate
   input  bit     vec_d_is_store[`MAX_NUM_LANES],
   input  int     vec_d_size[`MAX_NUM_LANES],
 
+  input  bit     inflight,
   output bit     finished
 );
 
@@ -43,6 +44,7 @@ module SimMemFuzzer #(parameter NUM_LANES = 4) (
   // TODO: d_mask
   // TODO: d_data
 
+  input                                        inflight,
   output                                       finished
 );
   // "in": verilog->C, "out": C->verilog
@@ -58,6 +60,7 @@ module SimMemFuzzer #(parameter NUM_LANES = 4) (
   bit     __out_d_valid [0:`MAX_NUM_LANES-1];
   bit     __out_d_is_store [0:`MAX_NUM_LANES-1];
   int     __out_d_size [0:`MAX_NUM_LANES-1];
+  bit     __out_inflight;
   bit     __in_finished;
 
   genvar g;
@@ -77,6 +80,7 @@ module SimMemFuzzer #(parameter NUM_LANES = 4) (
       assign __out_d_is_store[g] = d_is_store[g];
       assign __out_d_size[g] = d_size[`SIMMEM_LOGSIZE_WIDTH*g +: `SIMMEM_LOGSIZE_WIDTH];
     end
+    assign __out_inflight = inflight;
   endgenerate
   assign finished = __in_finished;
 
@@ -112,6 +116,7 @@ module SimMemFuzzer #(parameter NUM_LANES = 4) (
         __out_d_is_store,
         __out_d_size,
 
+        __out_inflight,
         __in_finished
       );
       for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
@@ -119,7 +124,7 @@ module SimMemFuzzer #(parameter NUM_LANES = 4) (
           $time, tid, __in_a_valid[tid], tid, __in_a_address[tid], tid, __in_d_ready[tid]);
       end
 
-      if ($time >= 64'd200000) begin
+      if (finished) begin
         $finish;
       end
     end
diff --git a/src/main/scala/radiance/memory/Coalescing.scala b/src/main/scala/radiance/memory/Coalescing.scala
index 9864537..4bcab30 100644
--- a/src/main/scala/radiance/memory/Coalescing.scala
+++ b/src/main/scala/radiance/memory/Coalescing.scala
@@ -114,11 +114,10 @@ case class CoalescerConfig(
     s"than the request queue depth (${reqQueueDepth})")
 }
 
-
 object DefaultCoalescerConfig extends CoalescerConfig(
   enable = true,
   numLanes = 4,
-  reqQueueDepth = 2, // 1-deep request queues
+  reqQueueDepth = 2,
   timeCoalWindowSize = 1,
   waitTimeout = 8,
   addressWidth = 24,
@@ -418,6 +417,7 @@ class CoalShiftQueue[T <: Data](gen: T, entries: Int, config: CoalescerConfig)
       c && !(io.invalidate.valid && inv)
     }
     .reduce(_ || _)
+  dontTouch(shiftHint)
   val syncedEnqValid = io.queue.enq.map(_.valid).reduce(_ || _)
   // valid && !ready means we enable enqueueing to a full queue, provided the
   // arbiter is taking away all remaining valid queue heads in the next cycle so
@@ -2123,6 +2123,8 @@ class MemFuzzerImp(
       )
     )
   )
+  val anyInflight = sourceGens.map(_.io.inflight).reduce(_ || _)
+  sim.io.inflight := anyInflight
 
   // Take requests off of the queue and generate TL requests
   (outer.laneNodes zip (laneReqs zip laneResps)).zipWithIndex.foreach {
@@ -2217,7 +2219,8 @@ class MemFuzzerImp(
   // }
 }
 
-class SimMemFuzzer(numLanes: Int) extends BlackBox
+class SimMemFuzzer(numLanes: Int)
+    extends BlackBox(Map("NUM_LANES" -> numLanes))
     with HasBlackBoxResource {
   val traceLineT = new TraceLine
   val addrW = traceLineT.address.getWidth
@@ -2226,6 +2229,7 @@ class SimMemFuzzer(numLanes: Int) extends BlackBox
   val io = IO(new Bundle {
     val clock = Input(Clock())
     val reset = Input(Bool())
+    val inflight = Input(Bool())
     val finished = Output(Bool())
 
     val a =