diff --git a/src/main/scala/rocket/VortexCore.scala b/src/main/scala/rocket/VortexCore.scala
index 06f7055..75195f7 100644
--- a/src/main/scala/rocket/VortexCore.scala
+++ b/src/main/scala/rocket/VortexCore.scala
@@ -103,6 +103,7 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
   // addResource("/vsrc/vortex/hw/syn/synopsys/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v")
   // addResource("/vsrc/vortex/hw/syn/modelsim/vortex_tb.v")
 
+
   addResource("/vsrc/vortex/hw/rtl/VX_gpu_pkg.sv")
 
   // addResource("/vsrc/vortex/hw/rtl/VX_cluster.sv")
@@ -164,14 +165,13 @@ class Vortex(tile: VortexTile)(implicit p: Parameters)
   // addResource("/vsrc/vortex/hw/rtl/mem/VX_gbar_arb.sv")
   // addResource("/vsrc/vortex/hw/rtl/mem/VX_gbar_bus_if.sv")
   // addResource("/vsrc/vortex/hw/rtl/mem/VX_gbar_unit.sv")
-  // Only used for caches
+  // mem_arb is used in VX_socket or VX_cache_cluster
   // addResource("/vsrc/vortex/hw/rtl/mem/VX_mem_arb.sv")
   addResource("/vsrc/vortex/hw/rtl/mem/VX_mem_bus_if.sv")
   // addResource("/vsrc/vortex/hw/rtl/mem/VX_mem_perf_if.sv")
   addResource("/vsrc/vortex/hw/rtl/mem/VX_shared_mem.sv")
   addResource("/vsrc/vortex/hw/rtl/mem/VX_smem_switch.sv")
 
-
   // tex_unit missing in Vortex 2.0
   // addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_sat.sv")
   // addResource("/vsrc/vortex/hw/rtl/tex_unit/VX_tex_stride.sv")
diff --git a/src/main/scala/tile/VortexTile.scala b/src/main/scala/tile/VortexTile.scala
index 74619fe..e10e88e 100644
--- a/src/main/scala/tile/VortexTile.scala
+++ b/src/main/scala/tile/VortexTile.scala
@@ -187,6 +187,8 @@ class VortexTile private (
       "We recommend setting nSrcIds to at least 16."
   )
 
+  val smemSourceWidth = 4 // FIXME: hardcoded
+
   val imemNodes = Seq.tabulate(1) { i =>
     TLClientNode(
       Seq(
@@ -228,6 +230,30 @@ class VortexTile private (
       )
     )
   }
+
+  val smemNodes = Seq.tabulate(numLanes) { i =>
+    TLClientNode(
+      Seq(
+        TLMasterPortParameters.v1(
+          clients = Seq(
+            TLMasterParameters.v1(
+              sourceId = IdRange(0, 1 << smemSourceWidth),
+              name = s"Vortex Core ${vortexParams.hartId} SharedMem Lane $i",
+              requestFifo = true,
+              supportsProbe =
+                TransferSizes(1, lazyCoreParamsView.coreDataBytes),
+              supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
+              supportsPutFull =
+                TransferSizes(1, lazyCoreParamsView.coreDataBytes),
+              supportsPutPartial =
+                TransferSizes(1, lazyCoreParamsView.coreDataBytes)
+            )
+          )
+        )
+      )
+    )
+  }
+
   // combine outgoing per-lane dmemNode into 1 idenity node
   //
   // NOTE: We need TLWidthWidget here because there might be a data width
@@ -298,6 +324,13 @@ class VortexTile private (
     }
   }
 
+  // Instantiate sharedmem
+  // TODO: parametrize
+  val sharedmem = LazyModule(new TLRAM(AddressSet(0xff000000L, 0x00ffffffL), beatBytes = 4 /*FIXME*/))
+  val smemXbar = LazyModule(new TLXbar)
+  smemNodes.foreach(smemXbar.node := _)
+  sharedmem.node :=* smemXbar.node
+
   if (vortexParams.useVxCache) {
     tlMasterXbar.node := TLWidthWidget(16) := memNode
   } else {