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Take filename from Configs for easier trace testing

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This commit is contained in:
Hansung Kim
2023-05-07 19:09:25 -07:00
parent c75eaaf727
commit 15889d7667
1 changed files with 10 additions and 10 deletions
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20
src/main/scala/tilelink/Coalescing.scala
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@@ -233,11 +233,13 @@ class CoalShiftQueue[T <: Data](gen: T, entries: Int, config: CoalescerConfig) e
})) }))
// shift hint is when the heads have no more coalescable left this or next cycle // shift hint is when the heads have no more coalescable left this or next cycle
val shiftHint = !(io.coalescable zip io.invalidate.bits.map(_(0))).map { case (c, i) => val shiftHint = !(io.coalescable zip io.invalidate.bits.map(_(0))).map { case (c, inv) =>
c && !(io.invalidate.valid && i) c && !(io.invalidate.valid && inv)
}.reduce(_ || _) }.reduce(_ || _)
val syncedEnqValid = io.queue.enq.map(_.valid).reduce(_ || _) val syncedEnqValid = io.queue.enq.map(_.valid).reduce(_ || _)
val syncedDeqValid = io.queue.deq.map(x => x.valid && !x.ready).reduce(_ || _) // valid and not fire // syncedDeqValidNextCycle being true means the arbiter has completed
// processing all of the ready-to-go requests.
val syncedDeqValidNextCycle = io.queue.deq.map(x => x.valid && !x.ready).reduce(_ || _) // valid and not fire
for (i <- 0 until config.numLanes) { for (i <- 0 until config.numLanes) {
val enq = io.queue.enq(i) val enq = io.queue.enq(i)
@@ -247,7 +249,7 @@ class CoalShiftQueue[T <: Data](gen: T, entries: Int, config: CoalescerConfig) e
ctrl.full := writePtr(i) === entries.U ctrl.full := writePtr(i) === entries.U
ctrl.empty := writePtr(i) === 0.U ctrl.empty := writePtr(i) === 0.U
// shift when no outstanding dequeue, no more coalescable chunks, and not empty // shift when no outstanding dequeue, no more coalescable chunks, and not empty
ctrl.shift := !syncedDeqValid && shiftHint && !ctrl.empty ctrl.shift := !syncedDeqValidNextCycle && shiftHint && !ctrl.empty
// dequeue is valid when: // dequeue is valid when:
// head entry is valid, has not been processed by downstream, and is not coalescable // head entry is valid, has not been processed by downstream, and is not coalescable
@@ -1629,10 +1631,7 @@ class DummyCoalescerTest(timeout: Int = 500000)(implicit p: Parameters)
} }
// tracedriver --> coalescer --> tracelogger --> tlram // tracedriver --> coalescer --> tracelogger --> tlram
class TLRAMCoalescerLogger(implicit p: Parameters) extends LazyModule { class TLRAMCoalescerLogger(filename: String)(implicit p: Parameters) extends LazyModule {
// val filename = "test.trace"
val filename = "vecadd.core1.thread4.trace"
// val filename = "nvbit.vecadd.n100000.filter_sm0.trace"
// TODO: use parameters for numLanes // TODO: use parameters for numLanes
val numLanes = defaultConfig.numLanes val numLanes = defaultConfig.numLanes
@@ -1674,13 +1673,14 @@ class TLRAMCoalescerLogger(implicit p: Parameters) extends LazyModule {
(coreSideLogger.module.io.reqBytes === coreSideLogger.module.io.respBytes), (coreSideLogger.module.io.reqBytes === coreSideLogger.module.io.respBytes),
"FAIL: requests and responses traffic to the coalescer do not match" "FAIL: requests and responses traffic to the coalescer do not match"
) )
printf("SUCCESS: coalescer response traffic matched requests!\n")
} }
} }
} }
class TLRAMCoalescerLoggerTest(timeout: Int = 500000)(implicit p: Parameters) class TLRAMCoalescerLoggerTest(filename: String, timeout: Int = 500000)(implicit p: Parameters)
extends UnitTest(timeout) { extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMCoalescerLogger).module) val dut = Module(LazyModule(new TLRAMCoalescerLogger(filename)).module)
dut.io.start := io.start dut.io.start := io.start
io.finished := dut.io.finished io.finished := dut.io.finished
} }