diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index e7a4ded..1933f33 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -1056,7 +1056,7 @@ class Uncoalescer(
     val sizeInBits = ((1.U << logSize) << 3.U).asUInt
     assert(
       (dataWidth > 0).B && (dataWidth.U % sizeInBits === 0.U),
-      s"coalesced data width ($dataWidth) not evenly divisible by core req size ($sizeInBits)"
+      cf"coalesced data width ($dataWidth) not evenly divisible by core req size ($sizeInBits)"
     )
 
     val numChunks = dataWidth / 32