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Instantiate coalescer inside VortexTile

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Currently runtime errors with unhandled D opcode inside coalescer.
This commit is contained in:
Hansung Kim
2023-10-23 15:01:03 -07:00
parent 2091ef686b
commit 0f9896e001
1 changed files with 68 additions and 127 deletions
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195
src/main/scala/tile/VortexTile.scala
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@@ -43,9 +43,9 @@ case class VortexTileParams(
} }
// TODO: move to VortexCore // TODO: move to VortexCore
// VortexTileParams extends from TileParams that require a `core: CoreParams` // VortexTileParams extends TileParams which require a `core: CoreParams`
// field, so VortexCoreParams needs to also extend from that, requiring all // field, so VortexCoreParams needs to extend from that, requiring all
// these fields to be initialized. TODO. // these fields to be initialized. Most of this is unnecessary though. TODO
case class VortexCoreParams( case class VortexCoreParams(
bootFreqHz: BigInt = 0, bootFreqHz: BigInt = 0,
useVM: Boolean = true, useVM: Boolean = true,
@@ -53,9 +53,9 @@ case class VortexCoreParams(
useSupervisor: Boolean = false, useSupervisor: Boolean = false,
useHypervisor: Boolean = false, useHypervisor: Boolean = false,
useDebug: Boolean = true, useDebug: Boolean = true,
useAtomics: Boolean = true, useAtomics: Boolean = false,
useAtomicsOnlyForIO: Boolean = false, useAtomicsOnlyForIO: Boolean = false,
useCompressed: Boolean = true, useCompressed: Boolean = false,
useRVE: Boolean = false, useRVE: Boolean = false,
useSCIE: Boolean = false, useSCIE: Boolean = false,
useBitManip: Boolean = false, useBitManip: Boolean = false,
@@ -121,6 +121,8 @@ class VortexTile private (
val slaveNode = TLIdentityNode() val slaveNode = TLIdentityNode()
val masterNode = visibilityNode val masterNode = visibilityNode
println(s"======= found CoalescerKey: ${q(CoalescerKey).get.dataBusWidth}")
// Memory-mapped region for HTIF communication // Memory-mapped region for HTIF communication
// We use fixed addresses instead of tohost/fromhost // We use fixed addresses instead of tohost/fromhost
val regDevice = new SimpleDevice("vortex-reg", Seq(s"vortex-reg${tileParams.hartId}")) val regDevice = new SimpleDevice("vortex-reg", Seq(s"vortex-reg${tileParams.hartId}"))
@@ -149,75 +151,76 @@ class VortexTile private (
beatBytes = lazyCoreParamsView.coreDataBytes, beatBytes = lazyCoreParamsView.coreDataBytes,
minLatency = 1)))*/ minLatency = 1)))*/
val numLanes = 4 // TODO: use Parameters for this val numLanes = p(SIMTCoreKey) match {
val sourceWidth = 4 // TODO: use Parameters for this case Some(simtParam) => simtParam.nLanes
case None => 4
}
val sourceWidth = p(SIMTCoreKey) match {
// TODO: respect coalescer newSrcIds
case Some(simtParam) => log2Ceil(simtParam.nSrcIds)
case None => 4
}
val imemNodes = Seq.tabulate(1) { i => val imemNodes = Seq.tabulate(1) { i =>
TLClientNode( TLClientNode(Seq(TLMasterPortParameters.v1(
Seq( clients = Seq(TLMasterParameters.v1(
TLMasterPortParameters.v1( sourceId = IdRange(0, 1 << sourceWidth),
clients = Seq( name = s"Vortex Core ${vortexParams.hartId} I-Mem $i",
TLMasterParameters.v1( requestFifo = true,
sourceId = IdRange(0, 1 << sourceWidth), supportsProbe =
name = s"Vortex Core ${vortexParams.hartId} I-Mem $i", TransferSizes(1, lazyCoreParamsView.coreDataBytes),
requestFifo = true, supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
supportsProbe = ))
TransferSizes(1, lazyCoreParamsView.coreDataBytes), )))
supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
)
)
)
)
)
} }
val dmemNodes = Seq.tabulate(numLanes) { i => val dmemNodes = Seq.tabulate(numLanes) { i =>
TLClientNode( TLClientNode(Seq(TLMasterPortParameters.v1(
Seq( clients = Seq(TLMasterParameters.v1(
TLMasterPortParameters.v1( sourceId = IdRange(0, 1 << sourceWidth),
clients = Seq( name = s"Vortex Core ${vortexParams.hartId} D-Mem Lane $i",
TLMasterParameters.v1( requestFifo = true,
sourceId = IdRange(0, 1 << sourceWidth), supportsProbe =
name = s"Vortex Core ${vortexParams.hartId} D-Mem Lane $i", TransferSizes(1, lazyCoreParamsView.coreDataBytes),
requestFifo = true, supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsProbe = supportsPutFull =
TransferSizes(1, lazyCoreParamsView.coreDataBytes), TransferSizes(1, lazyCoreParamsView.coreDataBytes),
supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes), supportsPutPartial =
supportsPutFull = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
TransferSizes(1, lazyCoreParamsView.coreDataBytes), ))
supportsPutPartial = )))
TransferSizes(1, lazyCoreParamsView.coreDataBytes)
)
)
)
)
)
} }
// combine outgoing per-lane dmemNode into 1 idenity node
val dmemAggregateNode = TLIdentityNode()
dmemNodes.foreach { n => dmemAggregateNode := n }
println(s"============= lazyCoreParamsView.coreDataBytes=${lazyCoreParamsView.coreDataBytes}") val memNode = TLClientNode(Seq(TLMasterPortParameters.v1(
val memNode = TLClientNode( clients = Seq(TLMasterParameters.v1(
Seq( sourceId = IdRange(0, 1 << sourceWidth),
TLMasterPortParameters.v1( name = s"Vortex Core ${vortexParams.hartId} Mem Interface",
clients = Seq( requestFifo = true,
TLMasterParameters.v1( supportsProbe = TransferSizes(16, 16), // FIXME: hardcoded
sourceId = IdRange(0, 1 << sourceWidth), supportsGet = TransferSizes(16, 16),
name = s"Vortex Core ${vortexParams.hartId} Mem Interface", supportsPutFull = TransferSizes(16, 16),
requestFifo = true, supportsPutPartial = TransferSizes(16, 16)
supportsProbe = TransferSizes(16, 16), // FIXME: hardcoded ))
supportsGet = TransferSizes(16, 16), )))
supportsPutFull = TransferSizes(16, 16),
supportsPutPartial = TransferSizes(16, 16) // Conditionally instantiate memory coalescer
) val coalescerNode = p(CoalescerKey) match {
) case Some(coalescerParam) => {
) val coal = LazyModule(new CoalescingUnit(coalescerParam))
) coal.cpuNode :=* dmemAggregateNode
) coal.aggregateNode // N+1 lanes
}
case None => dmemAggregateNode
}
if (vortexParams.useVxCache) { if (vortexParams.useVxCache) {
tlMasterXbar.node := TLWidthWidget(16) := memNode tlMasterXbar.node := TLWidthWidget(16) := memNode
} else { } else {
imemNodes.foreach { tlMasterXbar.node := _ } imemNodes.foreach { tlMasterXbar.node := _ }
dmemNodes.foreach { tlMasterXbar.node := _ } tlMasterXbar.node :=* coalescerNode
} }
/* below are copied from rocket */ /* below are copied from rocket */
@@ -427,71 +430,9 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
} }
} }
// core.io.fpu := DontCare // TODO: generalize for useVxCache
if (!outer.vortexParams.useVxCache) {
// TODO eliminate this redundancy }
// val h = dcachePorts.size
// val c = core.dcacheArbPorts
// val o = outer.nDCachePorts
// require(h == c, s"port list size was $h, core expected $c")
// require(h == o, s"port list size was $h, outer counted $o")
// TODO figure out how to move the below into their respective mix-ins
// dcacheArb.io.requestor <> dcachePorts.toSeq
}
/** VortexCore wraps around the Vortex BlackBox module and exposes TileLink
* nodes for the core-cache memory interface.
*/
class VortexCore(implicit p: Parameters) extends LazyModule {
val numLanes = 4 // TODO: use Parameters for this
val sourceWidth = 4 // TODO: use Parameters for this
// val imemNodes = Seq.tabulate(1) { i =>
// TLClientNode(
// Seq(
// TLMasterPortParameters.v1(
// clients = Seq(
// TLMasterParameters.v1(
// sourceId = IdRange(0, 1 << sourceWidth),
// name = s"Vortex Core ${vortexParams.hartId} I-Mem $i",
// requestFifo = true,
// supportsProbe =
// TransferSizes(1, lazyCoreParamsView.coreDataBytes),
// supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes)
// )
// )
// )
// )
// )
// }
// val dmemNodes = Seq.tabulate(numLanes) { i =>
// TLClientNode(
// Seq(
// TLMasterPortParameters.v1(
// clients = Seq(
// TLMasterParameters.v1(
// sourceId = IdRange(0, 1 << sourceWidth),
// name = s"Vortex Core ${vortexParams.hartId} D-Mem Lane $i",
// requestFifo = true,
// supportsProbe =
// TransferSizes(1, lazyCoreParamsView.coreDataBytes),
// supportsGet = TransferSizes(1, lazyCoreParamsView.coreDataBytes),
// supportsPutFull =
// TransferSizes(1, lazyCoreParamsView.coreDataBytes),
// supportsPutPartial =
// TransferSizes(1, lazyCoreParamsView.coreDataBytes)
// )
// )
// )
// )
// )
// }
lazy val module = new VortexCoreModuleImp(this)
}
class VortexCoreModuleImp(outer: VortexCore) extends LazyModuleImp(outer) {
} }
// Some @copypaste from CoalescerSourceGen. // Some @copypaste from CoalescerSourceGen.