From 0ebaed5f1be9613d9a28030f3b87e9ced4fc94eb Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Mon, 27 Feb 2023 14:40:49 -0800
Subject: [PATCH] Communicate trace cycle data from C++ to Chisel

---
 src/main/resources/csrc/SimMemTrace.cc   | 51 +++++++++++++-----------
 src/main/resources/vsrc/SimMemTrace.v    | 12 +++---
 src/main/scala/tilelink/Coalescing.scala |  6 +--
 3 files changed, 36 insertions(+), 33 deletions(-)

diff --git a/src/main/resources/csrc/SimMemTrace.cc b/src/main/resources/csrc/SimMemTrace.cc
index 7cc2f8a..91740ab 100644
--- a/src/main/resources/csrc/SimMemTrace.cc
+++ b/src/main/resources/csrc/SimMemTrace.cc
@@ -7,8 +7,21 @@
 #include <unistd.h>
 
 class MemTraceReader;
+
+// Global singleton instance of MemTraceReader
 static std::unique_ptr<MemTraceReader> reader;
 
+struct MemTraceLine {
+  bool valid = false;
+  unsigned long cycle = 0;
+  char loadstore[10];
+  int core_id = 0;
+  int thread_id = 0;
+  unsigned long address = 0;
+  unsigned long data = 0;
+  int data_size = 0;
+};
+
 class MemTraceReader {
 public:
   MemTraceReader(const std::string &filename) {
@@ -26,31 +39,23 @@ public:
     infile.close();
     printf("MemTraceReader destroyed\n");
   }
-  bool tick();
+  MemTraceLine tick();
 
   std::ifstream infile;
 };
 
-// Returns true if there is no more memory trace left to read.
-bool MemTraceReader::tick() {
-  std::string line;
-  long cycle = 0;
-  char loadstore[10]{0};
-  int core_id = 0;
-  int thread_id = 0;
-  unsigned long address = 0;
-  unsigned long data = 0;
-  int data_size = 0;
+MemTraceLine MemTraceReader::tick() {
+  MemTraceLine line;
 
-  if (!(infile >> cycle >> loadstore >> core_id >> thread_id
-        >> std::hex >>
-        address >> data >> std::dec >> data_size
-        )) {
-    return true;
+  line.valid = false;
+  if (infile >> line.cycle >> line.loadstore >> line.core_id >>
+      line.thread_id >> std::hex >> line.address >> line.data >> std::dec >>
+      line.data_size) {
+    line.valid = true;
+    printf("cycle: %ld\n", line.cycle);
   }
 
-  printf("cycle: %ld\n", cycle);
-  return false;
+  return line;
 }
 
 extern "C" void memtrace_init(const char *filename) {
@@ -60,13 +65,11 @@ extern "C" void memtrace_init(const char *filename) {
 
 extern "C" void memtrace_tick(unsigned char *trace_read_valid,
                               unsigned char trace_read_ready,
-                              char *trace_read_bits) {
-  *trace_read_bits = 42;
+                              unsigned long *trace_read_bits) {
+  auto line = reader->tick();
 
-  *trace_read_valid = 0;
-  if (reader->tick()) {
-    *trace_read_valid = 1;
-  }
+  *trace_read_valid = line.valid;
+  *trace_read_bits = line.cycle;
 
   return;
 }
diff --git a/src/main/resources/vsrc/SimMemTrace.v b/src/main/resources/vsrc/SimMemTrace.v
index 8c1a161..18537b1 100644
--- a/src/main/resources/vsrc/SimMemTrace.v
+++ b/src/main/resources/vsrc/SimMemTrace.v
@@ -1,4 +1,4 @@
-`define DATA_WIDTH 8
+`define DATA_WIDTH 64
 
 import "DPI-C" function void memtrace_init(
     input  string  filename
@@ -8,7 +8,7 @@ import "DPI-C" function void memtrace_tick
 (
     output bit     trace_read_valid,
     input  bit     trace_read_ready,
-    output byte    trace_read_bits
+    output longint trace_read_bits
 );
 
 module SimMemTrace  (
@@ -21,7 +21,7 @@ module SimMemTrace  (
 );
 
     bit __in_valid;
-    byte __in_bits;
+    longint __in_bits;
     string __uartlog;
     int __uartno;
 
@@ -39,10 +39,10 @@ module SimMemTrace  (
     // Evaluate the signals on the positive edge
     always @(posedge clock) begin
         if (reset) begin
-            __in_valid = 0;
+            __in_valid = 1'b0;
 
-            __in_valid_reg <= 0;
-            __in_bits_reg <= 0;
+            __in_valid_reg <= 1'b0;
+            __in_bits_reg <= `DATA_WIDTH'b0;
         end else begin
             memtrace_tick(
                 __in_valid,
diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala
index 69d6c59..082c7f5 100644
--- a/src/main/scala/tilelink/Coalescing.scala
+++ b/src/main/scala/tilelink/Coalescing.scala
@@ -32,9 +32,9 @@ with HasBlackBoxResource {
     val reset = Input(Bool())
 
     val trace_read = new Bundle {
-      val ready = Input(Bool())
       val valid = Output(Bool())
-      val bits = Output(UInt(8.W))
+      val ready = Input(Bool())
+      val bits = Output(UInt(64.W))
     }
   })
 
@@ -52,5 +52,5 @@ extends UnitTest(timeout) {
   sim.io.reset := reset.asBool
   sim.io.trace_read.ready := true.B
 
-  io.finished := sim.io.trace_read.valid
+  io.finished := !sim.io.trace_read.valid
 }