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Doc cleanup

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This commit is contained in:
Hansung Kim
2023-03-19 01:17:11 -07:00
parent 2e06898dc0
commit 08ce7dc57d
1 changed files with 11 additions and 14 deletions
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25
src/main/scala/tilelink/Coalescing.scala
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@@ -22,7 +22,7 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
// Identity node that captures the incoming TL requests and passes them // Identity node that captures the incoming TL requests and passes them
// through the other end, dropping coalesced requests. This node is what // through the other end, dropping coalesced requests. This node is what
// will be visible from the external nodes. // will be visible to upstream and downstream nodes.
val node = TLIdentityNode() val node = TLIdentityNode()
// Number of maximum in-flight coalesced requests. The upper bound of this // Number of maximum in-flight coalesced requests. The upper bound of this
@@ -40,8 +40,7 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
Seq(TLMasterPortParameters.v1(coalParam)) Seq(TLMasterPortParameters.v1(coalParam))
) )
// Connect master node as the first of the N+1-th inward edges of the // Connect master node as the first inward edge of the IdentityNode
// IdentityNode
node :=* coalescerNode node :=* coalescerNode
lazy val module = new Impl lazy val module = new Impl
@@ -170,13 +169,13 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
(node.in zip node.out)(0) match { (node.in zip node.out)(0) match {
case ((tlIn, edgeIn), (tlOut, _)) => case ((tlIn, edgeIn), (tlOut, _)) =>
assert( assert(
edgeIn.master.masters(0).name == "CoalescerNode", edgeIn.master.masters.length == 1 &&
edgeIn.master.masters(0).name == "CoalescerNode",
"First edge is not connected to the coalescer master node" "First edge is not connected to the coalescer master node"
) )
// TODO: do we need to do anything here?
tlOut.a <> tlIn.a tlOut.a <> tlIn.a
// No need to drop any incoming coalesced responses, so just passthrough
// to master node
tlIn.d <> tlOut.d tlIn.d <> tlOut.d
dontTouch(tlIn.d) dontTouch(tlIn.d)
dontTouch(tlOut.d) dontTouch(tlOut.d)
@@ -196,9 +195,9 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
// InflightCoalReqTable is a reservation station-like structure that records // InflightCoalReqTable is a reservation station-like structure that records
// for each unanswered coalesced request which lane the request originated // for each unanswered coalesced request which lane the request originated
// from, what their original sourceId were, etc. We use this info to split // from, what their original TileLink sourceId were, etc. We use this info to
// the coalesced response back to individual responses for each lanes with // split the coalesced response back to individual per-lane responses with the
// the right metadata. // right metadata.
class InflightCoalReqTable( class InflightCoalReqTable(
val numLanes: Int, val numLanes: Int,
val sourceWidth: Int, val sourceWidth: Int,
@@ -380,11 +379,9 @@ class MemTraceDriverImp(outer: MemTraceDriver, numLanes: Int)
val (plegal, pbits) = edge.Put( val (plegal, pbits) = edge.Put(
fromSource = sourceIdCounter, fromSource = sourceIdCounter,
toAddress = req.address, toAddress = req.address,
// Memory trace addresses are not aligned in word addresses (e.g. // Memory trace addresses are not necessarily aligned to word boundaries
// read of size 1 at 0x1007) so leave lgSize to 0. // so leave lgSize to 0
// TODO: We need to build an issue logic that aligns addresses at // NOTE: this is in bytes not bits
// word boundaries and uses masks.
// NOTE: this is in byte size, not bits
lgSize = 0.U, lgSize = 0.U,
data = req.data data = req.data
) )