Split out CoalescingUnitImp
This commit is contained in:
Hansung Kim
@@ -29,13 +29,18 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
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sourceId = IdRange(0, numInflightCoalRequests)
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sourceId = IdRange(0, numInflightCoalRequests)
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)
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)
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)
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)
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protected val coalescerNode = TLClientNode(
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val coalescerNode = TLClientNode(
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Seq(TLMasterPortParameters.v1(coalParam))
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Seq(TLMasterPortParameters.v1(coalParam))
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)
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)
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// Connect master node as the first inward edge of the IdentityNode
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// Connect master node as the first inward edge of the IdentityNode
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node :=* coalescerNode
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node :=* coalescerNode
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lazy val module = new CoalescingUnitImp(this, numLanes)
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}
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class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int)
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extends LazyModuleImp(outer) {
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class ReqQueueEntry(val sourceWidth: Int, val addressWidth: Int)
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class ReqQueueEntry(val sourceWidth: Int, val addressWidth: Int)
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extends Bundle {
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extends Bundle {
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val source = UInt(sourceWidth.W)
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val source = UInt(sourceWidth.W)
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@@ -47,208 +52,209 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
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val data = UInt(64.W /* FIXME hardcoded */ ) // read data
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val data = UInt(64.W /* FIXME hardcoded */ ) // read data
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}
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}
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lazy val module = new Impl
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// node.in(0) is from coalescer TL master node; 1~N are from cores
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class Impl extends LazyModuleImp(this) {
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// assert(node.in.length >= 2)
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// node.in(0) is from coalescer TL master node; 1~N are from cores
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val sourceWidth = outer.node.in(1)._1.params.sourceBits
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// assert(node.in.length >= 2)
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val addressWidth = outer.node.in(1)._1.params.addressBits
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val sourceWidth = node.in(1)._1.params.sourceBits
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val reqQueueEntryT = new ReqQueueEntry(sourceWidth, addressWidth)
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val addressWidth = node.in(1)._1.params.addressBits
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val reqQueues = Seq.tabulate(numLanes) { _ =>
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val reqQueueEntryT = new ReqQueueEntry(sourceWidth, addressWidth)
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Module(
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val reqQueues = Seq.tabulate(numLanes) { _ =>
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new ShiftQueue(reqQueueEntryT, 4 /* FIXME hardcoded */ )
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Module(
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new ShiftQueue(reqQueueEntryT, 4 /* FIXME hardcoded */ )
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)
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}
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val respQueueEntryT = new RespQueueEntry(sourceWidth)
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val respQueues = Seq.tabulate(numLanes) { _ =>
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Module(
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new ShiftQueue(respQueueEntryT, 8 /* FIXME hardcoded */ )
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)
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}
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// Per-lane request and response queues
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//
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// Override IdentityNode implementation so that we wire node output to the
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// queue output, instead of directly passing through node input.
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// See IdentityNode definition in `diplomacy/Nodes.scala`.
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(node.in zip node.out).zipWithIndex.foreach {
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case (((_, edgeIn), _), 0) =>
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// No need to do anything on the edge from coalescerNode
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assert(
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edgeIn.master.masters(0).name == "CoalescerNode",
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"First edge is not connected to the coalescer master node"
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)
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case (((tlIn, edgeIn), (tlOut, edgeOut)), i) =>
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// Request queue
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//
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val reqQueue = reqQueues(i - 1)
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val req = Wire(reqQueueEntryT)
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req.source := tlIn.a.bits.source
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req.address := tlIn.a.bits.address
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req.data := tlIn.a.bits.data
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println(s"============ req.source width=${req.source.widthOption.get}")
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reqQueue.io.enq.valid := tlIn.a.valid
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reqQueue.io.enq.bits := req
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// TODO: deq.ready should respect downstream ready
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reqQueue.io.deq.ready := true.B
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tlOut.a.valid := reqQueue.io.deq.valid
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val reqHead = reqQueue.io.deq.bits
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// FIXME: generate Get or Put according to read/write
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val (reqLegal, reqBits) = edgeOut.Get(
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fromSource = reqHead.source,
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// `toAddress` should be aligned to 2**lgSize
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toAddress = reqHead.address,
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lgSize = 0.U
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)
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assert(reqLegal, "unhandled illegal TL req gen")
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tlOut.a.bits := reqBits
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// Response queue
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//
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// This queue will serialize non-coalesced responses along with
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// coalesced responses and serve them back to the core side.
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val respQueue = respQueues(i - 1)
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val resp = Wire(respQueueEntryT)
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resp.source := tlOut.d.bits.source
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resp.data := tlOut.d.bits.data
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respQueue.io.enq.valid := tlOut.d.valid
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respQueue.io.enq.bits := resp
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// TODO: deq.ready should respect upstream ready
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respQueue.io.deq.ready := true.B
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tlIn.d.valid := respQueue.io.deq.valid
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val respHead = respQueue.io.deq.bits
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val respBits = edgeIn.AccessAck(
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toSource = respHead.source,
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lgSize = 0.U,
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data = respHead.data
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)
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tlIn.d.bits := respBits
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// tlIn.d <> tlOut.d
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// Debug only
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val inflightCounter = RegInit(UInt(32.W), 0.U)
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when(tlOut.a.valid) {
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// don't inc/dec on simultaneous req/resp
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when(!tlOut.d.valid) {
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inflightCounter := inflightCounter + 1.U
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}
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}.elsewhen(tlOut.d.valid) {
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inflightCounter := inflightCounter - 1.U
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}
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dontTouch(inflightCounter)
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dontTouch(tlIn.a)
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dontTouch(tlIn.d)
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dontTouch(tlOut.a)
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dontTouch(tlOut.d)
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}
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// Generate coalesced requests
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// FIXME: currently generating bogus coalesced requests
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val coalSourceId = RegInit(0.U(2.W /* FIXME hardcoded */ ))
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coalSourceId := coalSourceId + 1.U
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val (tlCoal, edgeCoal) = coalescerNode.out(0)
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val coalReqAddress = Wire(UInt(tlCoal.params.addressBits.W))
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// TODO: bogus address
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coalReqAddress := (0xabcd.U + coalSourceId) << 4
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val coalReqValid = Wire(Bool())
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// FIXME: copy lane 1's valid signal. This is completely bogus
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coalReqValid := node.in(1)._1.a.valid
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val (legal, bits) = edgeCoal.Get(
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fromSource = coalSourceId,
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// `toAddress` should be aligned to 2**lgSize
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toAddress = coalReqAddress,
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// 64 bits = 8 bytes = 2**(3) bytes
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lgSize = 3.U
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)
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)
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assert(legal, "unhandled illegal TL req gen")
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tlCoal.a.valid := coalReqValid
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tlCoal.a.bits := bits
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tlCoal.b.ready := true.B
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tlCoal.c.valid := false.B
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tlCoal.d.ready := true.B
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tlCoal.e.valid := false.B
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// Construct new entry for the inflight table
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val inflightTable = Module(
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new InflightCoalReqTable(numLanes, sourceWidth, numInflightCoalRequests)
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)
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val newEntry = Wire(inflightTable.entryT)
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newEntry.respSourceId := coalSourceId
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newEntry.lanes.foreach { l =>
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l.valid := false.B
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l.reqs.foreach { r =>
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// TODO: this part needs the actual coalescing logic to work
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r.valid := true.B
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r.offset := 1.U
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r.size := 2.U
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}
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}
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newEntry.lanes(0).valid := true.B
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newEntry.lanes(2).valid := true.B
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dontTouch(newEntry)
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// Populate inflight coalesced request table
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inflightTable.io.enq.valid := coalReqValid
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inflightTable.io.enq.bits := newEntry
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// Look up the table with incoming coalesced responses
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inflightTable.io.lookup.ready := tlCoal.d.valid
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inflightTable.io.lookupSourceId := tlCoal.d.bits.source
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val coalRespData = Wire(UInt(tlCoal.params.dataBits.W))
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coalRespData := tlCoal.d.bits.data
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when(inflightTable.io.lookup.valid) {
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val found = inflightTable.io.lookup.bits
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found.lanes.zipWithIndex.foreach { case (l, i) =>
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val respQueue = respQueues(i)
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respQueue.io.enq.valid := l.valid
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respQueue.io.enq.bits.source := 0.U // FIXME: only looking at 0th entry
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// FIXME: disregard size enum for now
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val sizeMask = (1.U << 4) - 1.U
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val dataWidth = tlCoal.params.dataBits
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// FIXME: handle multi-head input to the queue
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respQueue.io.enq.bits.data := (coalRespData >> (dataWidth - 4)) & sizeMask
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when(l.valid) {
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when(l.reqs(0).valid) {
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printf(s"lane ${i} req 0 is valid!\n")
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}
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}
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}
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}
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(node.in zip node.out)(0) match {
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case ((tlIn, edgeIn), (tlOut, _)) =>
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assert(
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edgeIn.master.masters.length == 1 &&
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edgeIn.master.masters(0).name == "CoalescerNode",
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"First edge is not connected to the coalescer master node"
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)
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// TODO: do we need to do anything here?
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tlOut.a <> tlIn.a
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tlIn.d <> tlOut.d
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dontTouch(tlIn.d)
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dontTouch(tlOut.d)
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}
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// Debug
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dontTouch(coalReqValid)
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dontTouch(coalReqAddress)
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dontTouch(coalRespData)
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dontTouch(tlCoal.a)
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dontTouch(tlCoal.d)
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}
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}
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val respQueueEntryT = new RespQueueEntry(sourceWidth)
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val respQueues = Seq.tabulate(numLanes) { _ =>
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Module(
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new ShiftQueue(respQueueEntryT, 8 /* FIXME hardcoded */ )
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)
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}
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// Per-lane request and response queues
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//
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// Override IdentityNode implementation so that we wire node output to the
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// queue output, instead of directly passing through node input.
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// See IdentityNode definition in `diplomacy/Nodes.scala`.
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(outer.node.in zip outer.node.out).zipWithIndex.foreach {
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case (((_, edgeIn), _), 0) =>
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// No need to do anything on the edge from coalescerNode
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assert(
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edgeIn.master.masters(0).name == "CoalescerNode",
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"First edge is not connected to the coalescer master node"
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)
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case (((tlIn, edgeIn), (tlOut, edgeOut)), i) =>
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// Request queue
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//
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val reqQueue = reqQueues(i - 1)
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val req = Wire(reqQueueEntryT)
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req.source := tlIn.a.bits.source
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req.address := tlIn.a.bits.address
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req.data := tlIn.a.bits.data
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println(s"============ req.source width=${req.source.widthOption.get}")
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reqQueue.io.enq.valid := tlIn.a.valid
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reqQueue.io.enq.bits := req
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// TODO: deq.ready should respect downstream ready
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reqQueue.io.deq.ready := true.B
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tlOut.a.valid := reqQueue.io.deq.valid
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val reqHead = reqQueue.io.deq.bits
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// FIXME: generate Get or Put according to read/write
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val (reqLegal, reqBits) = edgeOut.Get(
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fromSource = reqHead.source,
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// `toAddress` should be aligned to 2**lgSize
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toAddress = reqHead.address,
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lgSize = 0.U
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)
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assert(reqLegal, "unhandled illegal TL req gen")
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tlOut.a.bits := reqBits
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// Response queue
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//
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// This queue will serialize non-coalesced responses along with
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// coalesced responses and serve them back to the core side.
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val respQueue = respQueues(i - 1)
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val resp = Wire(respQueueEntryT)
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resp.source := tlOut.d.bits.source
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resp.data := tlOut.d.bits.data
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respQueue.io.enq.valid := tlOut.d.valid
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respQueue.io.enq.bits := resp
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// TODO: deq.ready should respect upstream ready
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respQueue.io.deq.ready := true.B
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tlIn.d.valid := respQueue.io.deq.valid
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val respHead = respQueue.io.deq.bits
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val respBits = edgeIn.AccessAck(
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toSource = respHead.source,
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lgSize = 0.U,
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data = respHead.data
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)
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tlIn.d.bits := respBits
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// tlIn.d <> tlOut.d
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// Debug only
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val inflightCounter = RegInit(UInt(32.W), 0.U)
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when(tlOut.a.valid) {
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// don't inc/dec on simultaneous req/resp
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when(!tlOut.d.valid) {
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inflightCounter := inflightCounter + 1.U
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}
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}.elsewhen(tlOut.d.valid) {
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inflightCounter := inflightCounter - 1.U
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}
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dontTouch(inflightCounter)
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dontTouch(tlIn.a)
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dontTouch(tlIn.d)
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dontTouch(tlOut.a)
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dontTouch(tlOut.d)
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}
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// Generate coalesced requests
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// FIXME: currently generating bogus coalesced requests
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||||||
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val coalSourceId = RegInit(0.U(2.W /* FIXME hardcoded */ ))
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coalSourceId := coalSourceId + 1.U
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val (tlCoal, edgeCoal) = outer.coalescerNode.out(0)
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val coalReqAddress = Wire(UInt(tlCoal.params.addressBits.W))
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// TODO: bogus address
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coalReqAddress := (0xabcd.U + coalSourceId) << 4
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val coalReqValid = Wire(Bool())
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// FIXME: copy lane 1's valid signal. This is completely bogus
|
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coalReqValid := outer.node.in(1)._1.a.valid
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val (legal, bits) = edgeCoal.Get(
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fromSource = coalSourceId,
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// `toAddress` should be aligned to 2**lgSize
|
||||||
|
toAddress = coalReqAddress,
|
||||||
|
// 64 bits = 8 bytes = 2**(3) bytes
|
||||||
|
lgSize = 3.U
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|
)
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assert(legal, "unhandled illegal TL req gen")
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tlCoal.a.valid := coalReqValid
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tlCoal.a.bits := bits
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tlCoal.b.ready := true.B
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tlCoal.c.valid := false.B
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tlCoal.d.ready := true.B
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tlCoal.e.valid := false.B
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// Construct new entry for the inflight table
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||||||
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val inflightTable = Module(
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|
new InflightCoalReqTable(
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||||||
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numLanes,
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||||||
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sourceWidth,
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||||||
|
outer.numInflightCoalRequests
|
||||||
|
)
|
||||||
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)
|
||||||
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val newEntry = Wire(inflightTable.entryT)
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||||||
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newEntry.respSourceId := coalSourceId
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||||||
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newEntry.lanes.foreach { l =>
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l.valid := false.B
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||||||
|
l.reqs.foreach { r =>
|
||||||
|
// TODO: this part needs the actual coalescing logic to work
|
||||||
|
r.valid := true.B
|
||||||
|
r.offset := 1.U
|
||||||
|
r.size := 2.U
|
||||||
|
}
|
||||||
|
}
|
||||||
|
newEntry.lanes(0).valid := true.B
|
||||||
|
newEntry.lanes(2).valid := true.B
|
||||||
|
dontTouch(newEntry)
|
||||||
|
|
||||||
|
// Populate inflight coalesced request table
|
||||||
|
inflightTable.io.enq.valid := coalReqValid
|
||||||
|
inflightTable.io.enq.bits := newEntry
|
||||||
|
|
||||||
|
// Look up the table with incoming coalesced responses
|
||||||
|
inflightTable.io.lookup.ready := tlCoal.d.valid
|
||||||
|
inflightTable.io.lookupSourceId := tlCoal.d.bits.source
|
||||||
|
val coalRespData = Wire(UInt(tlCoal.params.dataBits.W))
|
||||||
|
coalRespData := tlCoal.d.bits.data
|
||||||
|
|
||||||
|
when(inflightTable.io.lookup.valid) {
|
||||||
|
val found = inflightTable.io.lookup.bits
|
||||||
|
found.lanes.zipWithIndex.foreach { case (l, i) =>
|
||||||
|
val respQueue = respQueues(i)
|
||||||
|
respQueue.io.enq.valid := l.valid
|
||||||
|
respQueue.io.enq.bits.source := 0.U // FIXME: only looking at 0th entry
|
||||||
|
// FIXME: disregard size enum for now
|
||||||
|
val sizeMask = (1.U << 4) - 1.U
|
||||||
|
val dataWidth = tlCoal.params.dataBits
|
||||||
|
// FIXME: handle multi-head input to the queue
|
||||||
|
respQueue.io.enq.bits.data := (coalRespData >> (dataWidth - 4)) & sizeMask
|
||||||
|
|
||||||
|
when(l.valid) {
|
||||||
|
when(l.reqs(0).valid) {
|
||||||
|
printf(s"lane ${i} req 0 is valid!\n")
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
(outer.node.in zip outer.node.out)(0) match {
|
||||||
|
case ((tlIn, edgeIn), (tlOut, _)) =>
|
||||||
|
assert(
|
||||||
|
edgeIn.master.masters.length == 1 &&
|
||||||
|
edgeIn.master.masters(0).name == "CoalescerNode",
|
||||||
|
"First edge is not connected to the coalescer master node"
|
||||||
|
)
|
||||||
|
|
||||||
|
// TODO: do we need to do anything here?
|
||||||
|
tlOut.a <> tlIn.a
|
||||||
|
tlIn.d <> tlOut.d
|
||||||
|
dontTouch(tlIn.d)
|
||||||
|
dontTouch(tlOut.d)
|
||||||
|
}
|
||||||
|
|
||||||
|
// Debug
|
||||||
|
dontTouch(coalReqValid)
|
||||||
|
dontTouch(coalReqAddress)
|
||||||
|
dontTouch(coalRespData)
|
||||||
|
|
||||||
|
dontTouch(tlCoal.a)
|
||||||
|
dontTouch(tlCoal.d)
|
||||||
}
|
}
|
||||||
|
|
||||||
// InflightCoalReqTable is a reservation station-like structure that records
|
// InflightCoalReqTable is a reservation station-like structure that records
|
||||||
|
|||||||
Reference in New Issue
Block a user