Split out CoalescingUnitImp

src/main/scala/tilelink/Coalescing.scala

@@ -29,13 +29,18 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
       sourceId = IdRange(0, numInflightCoalRequests)
     )
   )
-  protected val coalescerNode = TLClientNode(
+  val coalescerNode = TLClientNode(
     Seq(TLMasterPortParameters.v1(coalParam))
   )
 
   // Connect master node as the first inward edge of the IdentityNode
   node :=* coalescerNode
 
+  lazy val module = new CoalescingUnitImp(this, numLanes)
+}
+
+class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int)
+    extends LazyModuleImp(outer) {
   class ReqQueueEntry(val sourceWidth: Int, val addressWidth: Int)
       extends Bundle {
     val source = UInt(sourceWidth.W)
@@ -47,12 +52,10 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
     val data = UInt(64.W /* FIXME hardcoded */ ) // read data
   }
 
-  lazy val module = new Impl
-  class Impl extends LazyModuleImp(this) {
   // node.in(0) is from coalescer TL master node; 1~N are from cores
   // assert(node.in.length >= 2)
-    val sourceWidth = node.in(1)._1.params.sourceBits
+  val sourceWidth = outer.node.in(1)._1.params.sourceBits
-    val addressWidth = node.in(1)._1.params.addressBits
+  val addressWidth = outer.node.in(1)._1.params.addressBits
   val reqQueueEntryT = new ReqQueueEntry(sourceWidth, addressWidth)
   val reqQueues = Seq.tabulate(numLanes) { _ =>
     Module(
@@ -71,7 +74,7 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
   // Override IdentityNode implementation so that we wire node output to the
   // queue output, instead of directly passing through node input.
   // See IdentityNode definition in `diplomacy/Nodes.scala`.
-    (node.in zip node.out).zipWithIndex.foreach {
+  (outer.node.in zip outer.node.out).zipWithIndex.foreach {
     case (((_, edgeIn), _), 0) =>
       // No need to do anything on the edge from coalescerNode
       assert(
@@ -154,13 +157,13 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
   val coalSourceId = RegInit(0.U(2.W /* FIXME hardcoded */ ))
   coalSourceId := coalSourceId + 1.U
 
-    val (tlCoal, edgeCoal) = coalescerNode.out(0)
+  val (tlCoal, edgeCoal) = outer.coalescerNode.out(0)
   val coalReqAddress = Wire(UInt(tlCoal.params.addressBits.W))
   // TODO: bogus address
   coalReqAddress := (0xabcd.U + coalSourceId) << 4
   val coalReqValid = Wire(Bool())
   // FIXME: copy lane 1's valid signal.  This is completely bogus
-    coalReqValid := node.in(1)._1.a.valid
+  coalReqValid := outer.node.in(1)._1.a.valid
 
   val (legal, bits) = edgeCoal.Get(
     fromSource = coalSourceId,
@@ -179,7 +182,11 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
 
   // Construct new entry for the inflight table
   val inflightTable = Module(
-      new InflightCoalReqTable(numLanes, sourceWidth, numInflightCoalRequests)
+    new InflightCoalReqTable(
+      numLanes,
+      sourceWidth,
+      outer.numInflightCoalRequests
+    )
   )
   val newEntry = Wire(inflightTable.entryT)
   newEntry.respSourceId := coalSourceId
@@ -226,7 +233,7 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
     }
   }
 
-    (node.in zip node.out)(0) match {
+  (outer.node.in zip outer.node.out)(0) match {
     case ((tlIn, edgeIn), (tlOut, _)) =>
       assert(
         edgeIn.master.masters.length == 1 &&
@@ -248,7 +255,6 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
 
   dontTouch(tlCoal.a)
   dontTouch(tlCoal.d)
-  }
 }
 
 // InflightCoalReqTable is a reservation station-like structure that records