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Fix wrong width for lookup srcId in InFlightTable

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This commit is contained in:
Hansung Kim
2024-02-06 22:33:51 -08:00
parent 7cfa994890
commit 0384324e83
1 changed files with 2 additions and 8 deletions
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10
src/main/scala/radiance/memory/Coalescing.scala
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@@ -1297,7 +1297,7 @@ class InFlightTable(
config.sizeEnum config.sizeEnum
) )
val entries = config.numNewSrcIds val entries = config.numNewSrcIds
val sourceWidth = log2Ceil(config.numOldSrcIds) val newSourceWidth = log2Ceil(config.numNewSrcIds)
val io = IO(new Bundle { val io = IO(new Bundle {
// Enqueue/register IO // Enqueue/register IO
@@ -1324,18 +1324,12 @@ class InFlightTable(
// //
// Initiates table lookup via (valid, sourceId). The lookup result will be // Initiates table lookup via (valid, sourceId). The lookup result will be
// placed on lookupResult. // placed on lookupResult.
val lookupSourceId = Input(Valid(UInt(sourceWidth.W))) val lookupSourceId = Input(Valid(UInt(newSourceWidth.W)))
// lookupResult.ready indicates when the user module consumed the table // lookupResult.ready indicates when the user module consumed the table
// entry, so that the entry can be safely deallocated for later use. // entry, so that the entry can be safely deallocated for later use.
val lookupResult = Decoupled(entryT) val lookupResult = Decoupled(entryT)
}) })
println(s"CoalescingUnit InFlightTable config: {")
println(s" sourceWidth: ${sourceWidth}")
println(s" offsetBits: ${offsetBits}")
println(s" sizeEnumBits: ${entryT.sizeEnumT.getWidth}")
println(s"}")
val table = Mem( val table = Mem(
entries, entries,
new Bundle { new Bundle {