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Fix width mismatch for source logger

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This commit is contained in:
Hansung Kim
2023-04-17 18:52:38 -07:00
parent d4a51cfee5
commit 02ce969c67
2 changed files with 12 additions and 10 deletions
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2
src/main/resources/csrc/SimMemTraceLogger.cc
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@@ -35,7 +35,7 @@ MemTraceWriter::~MemTraceWriter() {
} }
void MemTraceWriter::write_line_to_trace(const MemTraceLine line) { void MemTraceWriter::write_line_to_trace(const MemTraceLine line) {
fprintf(outfile, "%ld %s %d %d %d, 0x%lx 0x%lx %u\n", line.cycle, fprintf(outfile, "%ld %s %d %d %d 0x%lx 0x%lx %u\n", line.cycle,
(line.is_store ? "STORE" : "LOAD"), line.core_id, line.lane_id, (line.is_store ? "STORE" : "LOAD"), line.core_id, line.lane_id,
line.source, line.address, line.data, (1u << line.log_data_size)); line.source, line.address, line.data, (1u << line.log_data_size));
} }

20
src/main/scala/tilelink/Coalescing.scala
View File

@@ -824,6 +824,7 @@ class MemTraceLogger(
req.size := tlIn.a.bits.size req.size := tlIn.a.bits.size
req.is_store := tlAOpcodeIsStore(tlIn.a.bits.opcode) req.is_store := tlAOpcodeIsStore(tlIn.a.bits.opcode)
req.source := tlIn.a.bits.source req.source := tlIn.a.bits.source
printf("======== req.source=%d\n", req.source)
// TL always carries the exact unaligned address that the client // TL always carries the exact unaligned address that the client
// originally requested, so no postprocessing required // originally requested, so no postprocessing required
req.address := tlIn.a.bits.address req.address := tlIn.a.bits.address
@@ -863,6 +864,7 @@ class MemTraceLogger(
resp.size := tlOut.d.bits.size resp.size := tlOut.d.bits.size
resp.is_store := tlDOpcodeIsStore(tlOut.d.bits.opcode) resp.is_store := tlDOpcodeIsStore(tlOut.d.bits.opcode)
resp.source := tlOut.d.bits.source resp.source := tlOut.d.bits.source
printf("======== resp.source=%d\n", resp.source)
// NOTE: TL D channel doesn't carry address nor mask, so there's no easy // NOTE: TL D channel doesn't carry address nor mask, so there's no easy
// way to figure out which bytes the master actually use. Since we // way to figure out which bytes the master actually use. Since we
// don't care too much about addresses in the trace anyway, just store // don't care too much about addresses in the trace anyway, just store
@@ -876,19 +878,19 @@ class MemTraceLogger(
// assignment to a bitfield range of a wide signal. // assignment to a bitfield range of a wide signal.
def flattenTrace(traceLogIO: Bundle with HasTraceLine, perLane: Vec[TraceLine]) = { def flattenTrace(traceLogIO: Bundle with HasTraceLine, perLane: Vec[TraceLine]) = {
// these will get optimized out // these will get optimized out
val vecValid = Wire(Vec(numLanes, Bool())) val vecValid = Wire(Vec(numLanes, chiselTypeOf(perLane(0).valid)))
val vecSource = Wire(Vec(numLanes, Bool())) val vecSource = Wire(Vec(numLanes, chiselTypeOf(perLane(0).source)))
val vecAddress = Wire(Vec(numLanes, chiselTypeOf(perLane(0).address))) val vecAddress = Wire(Vec(numLanes, chiselTypeOf(perLane(0).address)))
val vecIsStore = Wire(Vec(numLanes, chiselTypeOf(perLane(0).is_store))) val vecIsStore = Wire(Vec(numLanes, chiselTypeOf(perLane(0).is_store)))
val vecSize = Wire(Vec(numLanes, chiselTypeOf(perLane(0).size))) val vecSize = Wire(Vec(numLanes, chiselTypeOf(perLane(0).size)))
val vecData = Wire(Vec(numLanes, chiselTypeOf(perLane(0).data))) val vecData = Wire(Vec(numLanes, chiselTypeOf(perLane(0).data)))
perLane.zipWithIndex.foreach { case (req, i) => perLane.zipWithIndex.foreach { case (l, i) =>
vecValid(i) := req.valid vecValid(i) := l.valid
vecSource(i) := req.source vecSource(i) := l.source
vecAddress(i) := req.address vecAddress(i) := l.address
vecIsStore(i) := req.is_store vecIsStore(i) := l.is_store
vecSize(i) := req.size vecSize(i) := l.size
vecData(i) := req.data vecData(i) := l.data
} }
traceLogIO.valid := vecValid.asUInt traceLogIO.valid := vecValid.asUInt
traceLogIO.source := vecSource.asUInt traceLogIO.source := vecSource.asUInt