103 lines
2.8 KiB
Verilog
103 lines
2.8 KiB
Verilog
`include "VX_define.vh"
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module VX_divide #(
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parameter WIDTHN = 1,
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parameter WIDTHD = 1,
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parameter REP = "UNSIGNED",
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parameter PIPELINE = 0
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) (
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input wire clk,
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input wire reset,
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input wire clken,
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input [WIDTHN-1:0] numer,
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input [WIDTHD-1:0] denom,
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output reg [WIDTHN-1:0] quotient,
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output reg [WIDTHD-1:0] remainder
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);
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`ifdef QUARTUS
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lpm_divide #(
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.LPM_WIDTHN(WIDTHN),
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.LPM_WIDTHD(WIDTHD),
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.LPM_NREPRESENTATION(REP),
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.LPM_DREPRESENTATION(REP),
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.LPM_PIPELINE(PIPELINE),
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.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
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.MAXIMIZE_SPEED(9)
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) quartus_divider (
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.clock(clk),
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.aclr(reset),
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.clken(clken),
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.numer(numer),
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.denom(denom),
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.quotient(quotient),
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.remain(remainder)
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);
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`else
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wire [WIDTHN-1:0] numer_pipe_end;
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wire [WIDTHD-1:0] denom_pipe_end;
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if (PIPELINE == 0) begin
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assign numer_pipe_end = numer;
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assign denom_pipe_end = denom;
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end else begin
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reg [WIDTHN-1:0] numer_pipe [0:PIPELINE-1];
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reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
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genvar i;
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for (i = 0; i < PIPELINE; i++) begin
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always @(posedge clk) begin
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if (reset) begin
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numer_pipe[i] <= 0;
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denom_pipe[i] <= 0;
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end
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else if (clken) begin
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if (i == 0) begin
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numer_pipe[0] <= numer;
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denom_pipe[0] <= denom;
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end else begin
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numer_pipe[i] <= numer_pipe[i-1];
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denom_pipe[i] <= denom_pipe[i-1];
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end
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end
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end
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end
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assign numer_pipe_end = numer_pipe[PIPELINE-1];
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assign denom_pipe_end = denom_pipe[PIPELINE-1];
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end
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always @(*) begin
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if (denom_pipe_end == 0) begin
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quotient = {WIDTHN{1'b1}};
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remainder = numer_pipe_end;
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end
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`ifndef SYNTHESIS
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// this edge case kills verilator in some cases by causing a division
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// overflow exception. INT_MIN / -1 (on x86)
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else if (numer_pipe_end == {1'b1, (WIDTHN-1)'(0)}
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&& denom_pipe_end == {WIDTHD{1'b1}}) begin
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quotient = 0;
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remainder = 0;
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end
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`endif
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else begin
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if (REP == "SIGNED") begin
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quotient = $signed(numer_pipe_end) / $signed(denom_pipe_end);
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remainder = $signed(numer_pipe_end) % $signed(denom_pipe_end);
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end else begin
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quotient = numer_pipe_end / denom_pipe_end;
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remainder = numer_pipe_end % denom_pipe_end;
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end
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end
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end
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`endif
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endmodule : VX_divide
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