120 lines
4.0 KiB
Verilog
120 lines
4.0 KiB
Verilog
`include "VX_define.vh"
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module VX_dcache_arb (
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input wire clk,
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input wire reset,
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// input request
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VX_cache_core_req_if core_req_if,
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// output requests
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VX_cache_core_req_if cache_req_if,
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VX_cache_core_req_if smem_req_if,
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VX_cache_core_req_if io_req_if,
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// input responses
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VX_cache_core_rsp_if cache_rsp_if,
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VX_cache_core_rsp_if smem_rsp_if,
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VX_cache_core_rsp_if io_rsp_if,
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// output response
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VX_cache_core_rsp_if core_rsp_if
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);
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localparam REQ_DATAW = `NUM_THREADS + 1 + `NUM_THREADS * `DWORD_SIZE + `NUM_THREADS * (32-`CLOG2(`DWORD_SIZE)) + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
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localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
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//
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// select request
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//
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// select shared memory bus
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wire is_smem_addr = (| core_req_if.valid)
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&& ({core_req_if.addr[0], 2'b0} >= `SHARED_MEM_BASE_ADDR)
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&& ({core_req_if.addr[0], 2'b0} < (`SHARED_MEM_BASE_ADDR + `SMEM_SIZE));
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// select io bus
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wire is_io_addr = (| core_req_if.valid)
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&& ({core_req_if.addr[0], 2'b0} >= `IO_BUS_BASE_ADDR);
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reg [2:0] req_select;
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reg req_ready;
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assign cache_req_if.valid = core_req_if.valid & {`NUM_THREADS{req_select[0]}};
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assign cache_req_if.rw = core_req_if.rw;
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assign cache_req_if.byteen = core_req_if.byteen;
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assign cache_req_if.addr = core_req_if.addr;
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assign cache_req_if.data = core_req_if.data;
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assign cache_req_if.tag = core_req_if.tag;
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assign smem_req_if.valid = core_req_if.valid & {`NUM_THREADS{req_select[1]}};
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assign smem_req_if.rw = core_req_if.rw;
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assign smem_req_if.byteen = core_req_if.byteen;
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assign smem_req_if.addr = core_req_if.addr;
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assign smem_req_if.data = core_req_if.data;
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assign smem_req_if.tag = core_req_if.tag;
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assign io_req_if.valid = core_req_if.valid & {`NUM_THREADS{req_select[2]}};
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assign io_req_if.rw = core_req_if.rw;
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assign io_req_if.byteen = core_req_if.byteen;
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assign io_req_if.addr = core_req_if.addr;
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assign io_req_if.data = core_req_if.data;
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assign io_req_if.tag = core_req_if.tag;
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assign core_req_if.ready = req_ready;
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always @(*) begin
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req_select = 0;
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if (is_smem_addr) begin
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req_select[1] = 1;
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req_ready = smem_req_if.ready;
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end else if (is_io_addr) begin
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req_select[2] = 1;
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req_ready = io_req_if.ready;
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end else begin
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req_select[0] = 1;
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req_ready = cache_req_if.ready;
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end
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end
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//
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// select response
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//
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wire [2:0][RSP_DATAW-1:0] rsp_data_in;
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wire [2:0] rsp_valid_in;
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wire [2:0] rsp_ready_in;
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wire core_rsp_valid;
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wire [`NUM_THREADS-1:0] core_rsp_tmask;
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assign rsp_data_in[0] = {cache_rsp_if.valid, cache_rsp_if.data, cache_rsp_if.tag};
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assign rsp_data_in[1] = {smem_rsp_if.valid, smem_rsp_if.data, smem_rsp_if.tag};
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assign rsp_data_in[2] = {io_rsp_if.valid, io_rsp_if.data, io_rsp_if.tag};
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assign rsp_valid_in[0] = (| cache_rsp_if.valid);
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assign rsp_valid_in[1] = (| smem_rsp_if.valid);
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assign rsp_valid_in[2] = (| io_rsp_if.valid);
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VX_stream_arbiter #(
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.NUM_REQS (3),
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.DATAW (RSP_DATAW),
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.IN_BUFFER (1),
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.OUT_BUFFER (1)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (rsp_valid_in),
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.data_in (rsp_data_in),
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.ready_in (rsp_ready_in),
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.valid_out (core_rsp_valid),
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.data_out ({core_rsp_tmask, core_rsp_if.data, core_rsp_if.tag}),
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.ready_out (core_rsp_if.ready)
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);
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assign cache_rsp_if.ready = rsp_ready_in[0];
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assign smem_rsp_if.ready = rsp_ready_in[1];
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assign io_rsp_if.ready = rsp_ready_in[2];
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assign core_rsp_if.valid = core_rsp_tmask & {`NUM_THREADS{core_rsp_valid}};
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endmodule |