188 lines
6.8 KiB
Systemverilog
188 lines
6.8 KiB
Systemverilog
`include "VX_define.vh"
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`define FREG(x) {1'b1, `NRI_BITS'(`CLOG2(x))}
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module VX_uop_sequencer import VX_gpu_pkg::*; (
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input clk,
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input reset,
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VX_ibuffer_if.slave uop_sequencer_if,
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VX_ibuffer_if.master ibuffer_if
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);
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`ifdef EXT_T_ENABLE
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localparam UOP_TABLE_SIZE = 64;
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localparam UPC_BITS = `CLOG2(UOP_TABLE_SIZE);
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localparam NEXT = 2'b00;
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localparam FINISH = 2'b01;
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localparam UBR_BITS = 2;
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// uop metadata (sequencing, next state), execution metadata (EX_TYPE, OP_TYPE, OP_MOD), wb, use pc, use imm, pc, imm, rd, rs1, rs2, rs3
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localparam UOP_TABLE_WIDTH = UBR_BITS + UPC_BITS + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + 1 + `XLEN + `XLEN + (`NR_BITS * 4);
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localparam IBUFFER_IF_DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `XLEN + 1 + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + 1 + `XLEN + (`NR_BITS * 4);
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logic [UOP_TABLE_WIDTH-1:0] uop;
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// reserve space at start of table for more uop sequences
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localparam HMMA_SET0_STEP0_0 = UPC_BITS'(0);
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localparam HMMA_SET0_STEP0_1 = UPC_BITS'(8);
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/*
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localparam HMMA_SET0_STEP1_0 = UPC_BITS'(9);
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localparam HMMA_SET0_STEP1_1 = UPC_BITS'(10);
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localparam HMMA_SET0_STEP2_0 = UPC_BITS'(11);
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localparam HMMA_SET0_STEP2_1 = UPC_BITS'(12);
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localparam HMMA_SET0_STEP3_0 = UPC_BITS'(13);
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localparam HMMA_SET0_STEP3_1 = UPC_BITS'(14);
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localparam HMMA_SET1_STEP0_0 = UPC_BITS'(15);
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localparam HMMA_SET1_STEP0_1 = UPC_BITS'(16);
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localparam HMMA_SET1_STEP1_0 = UPC_BITS'(17);
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localparam HMMA_SET1_STEP1_1 = UPC_BITS'(18);
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localparam HMMA_SET1_STEP2_0 = UPC_BITS'(19);
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localparam HMMA_SET1_STEP2_1 = UPC_BITS'(20);
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localparam HMMA_SET1_STEP3_0 = UPC_BITS'(21);
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localparam HMMA_SET1_STEP3_1 = UPC_BITS'(22);
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localparam HMMA_SET2_STEP0_0 = UPC_BITS'(23);
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localparam HMMA_SET2_STEP0_1 = UPC_BITS'(24);
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localparam HMMA_SET2_STEP1_0 = UPC_BITS'(25);
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localparam HMMA_SET2_STEP1_1 = UPC_BITS'(26);
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localparam HMMA_SET2_STEP2_0 = UPC_BITS'(27);
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localparam HMMA_SET2_STEP2_1 = UPC_BITS'(28);
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localparam HMMA_SET2_STEP3_0 = UPC_BITS'(29);
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localparam HMMA_SET2_STEP3_1 = UPC_BITS'(30);
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localparam HMMA_SET3_STEP0_0 = UPC_BITS'(31);
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localparam HMMA_SET3_STEP0_1 = UPC_BITS'(32);
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localparam HMMA_SET3_STEP1_0 = UPC_BITS'(33);
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localparam HMMA_SET3_STEP1_1 = UPC_BITS'(34);
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localparam HMMA_SET3_STEP2_0 = UPC_BITS'(35);
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localparam HMMA_SET3_STEP2_1 = UPC_BITS'(36);
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localparam HMMA_SET3_STEP3_0 = UPC_BITS'(37);
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localparam HMMA_SET3_STEP3_1 = UPC_BITS'(38);
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*/
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// register layout: f0-f7 used for A, f8-f15 used for B, f16-f23 used for C
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always @(*) begin
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case (upc)
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HMMA_SET0_STEP0_0: begin
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uop = {
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NEXT,
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HMMA_SET0_STEP0_1,
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`EX_BITS'(`EX_TENSOR),
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`INST_OP_BITS'(0), // denotes that the first half is being computed
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`INST_MOD_BITS'(0), // field is unused for HMMA
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1'b1, // write back
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1'b0, // don't use PC
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1'b0, // don't use immediate
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32'b0, // PC is unused - TODO: don't send a bogus PC down the pipeline as it is very confusing in trace
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32'b0, // immediate is unused
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`FREG(16), // rd=f16
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`FREG(0), // rs1=f0,
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`FREG(8), // rs2=f8
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`FREG(16) // rs3=f16
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};
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end
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HMMA_SET0_STEP0_1: begin
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uop = {
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FINISH,
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HMMA_SET0_STEP0_0,
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`EX_BITS'(`EX_TENSOR),
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`INST_OP_BITS'(1), // denotes that the second half is being computed
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`INST_MOD_BITS'(0), // field is unused for HMMA
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1'b1, // write back
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1'b0, // don't use PC
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1'b0, // don't use immediate
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32'b0, // PC is unused - TODO: don't send a bogus PC down the pipeline as it is very confusing in trace
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32'b0, // immediate is unused
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`FREG(17), // rd=f17
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`FREG(1), // rs1=f1,
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`FREG(9), // rs2=f9
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`FREG(17) // rs3=f17
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};
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end
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default: begin
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uop = '0;
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end
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endcase
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end
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logic [UPC_BITS-1:0] upc, upc_r, upc_n;
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logic [UBR_BITS-1:0] ubr = uop[UOP_TABLE_WIDTH-1:UOP_TABLE_WIDTH-UBR_BITS];
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logic [UPC_BITS-1:0] next_upc = uop[UOP_TABLE_WIDTH-UBR_BITS-1:UOP_TABLE_WIDTH-UBR_BITS-UPC_BITS];
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logic uop_fire = use_uop && ibuffer_if.valid && ibuffer_if.ready;
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logic uop_start = ~use_uop_1d && use_uop;
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logic uop_finish = use_uop && uop_sequencer_if.valid && uop_sequencer_if.ready;
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logic use_uop, use_uop_1d;
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// merging the 2 always blocks leads to spurious UNOPTFLAT verilator lint, but conceptually they should be linked
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always @(*) begin
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use_uop = uop_sequencer_if.valid && uop_sequencer_if.data.ex_type == `EX_TENSOR;
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if (uop_start) begin
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// 1st cycle of microcoded operation, use op_type to determine entry point into microcode table
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upc_n = UPC_BITS'(uop_sequencer_if.data.op_type);
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end
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else begin
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upc_n = upc;
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end
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if (uop_fire) begin
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upc_n = next_upc;
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end
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end
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always @(*) begin
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if (uop_start) begin
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// 1st cycle of microcoded operation, use op_type to determine entry point into microcode table
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upc = UPC_BITS'(uop_sequencer_if.data.op_type);
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end
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else begin
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upc = upc_r;
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end
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end
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// copy UUID, wis, tmask from microcoded instruction
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logic [IBUFFER_IF_DATAW-1:0] ibuffer_output = {
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uop_sequencer_if.data.uuid,
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uop_sequencer_if.data.wis,
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uop_sequencer_if.data.tmask,
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uop[UOP_TABLE_WIDTH-UBR_BITS-UPC_BITS-1:0]
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};
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assign ibuffer_if.valid = use_uop ? 1'b1 : uop_sequencer_if.valid;
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assign uop_sequencer_if.ready = use_uop ? (uop_fire && ubr == FINISH) : ibuffer_if.ready;
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assign ibuffer_if.data = use_uop ? ibuffer_output : uop_sequencer_if.data;
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always @(posedge clk) begin
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if (reset) begin
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upc_r <= '0;
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use_uop_1d <= '0;
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end
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else begin
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upc_r <= upc_n;
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if (uop_finish) begin
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use_uop_1d <= 1'b0; // allow microcoded instructions to start immediately after eachother
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end
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else begin
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use_uop_1d <= use_uop;
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end
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end
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end
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`else
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`UNUSED_VAR(clk);
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`UNUSED_VAR(reset);
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assign ibuffer_if.valid = uop_sequencer_if.valid;
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assign uop_sequencer_if.ready = ibuffer_if.ready;
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assign ibuffer_if.data = uop_sequencer_if.data;
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`endif
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endmodule
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