127 lines
4.7 KiB
Verilog
127 lines
4.7 KiB
Verilog
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`include "../VX_define.h"
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// ========================================= Configurable Knobs =========================================
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// General Cache Knobs
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// Size of cache in bytes
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`define CACHE_SIZE_BYTES 1024
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// Size of line inside a bank in bytes
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`define BANK_LINE_SIZE_BYTES 16
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// Number of banks
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`define NUMBER_BANKS 8
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// Size of a word in bytes
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`define WORD_SIZE_BYTES 4
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// Number of Word requests per cycle
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`define NUMBER_REQUESTS `NT
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// Number of cycles to complete stage 2 (read from memory)
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`define STAGE_2_CYCLES 1
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// Queues feeding into banks Knobs
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// Core Request Queue Size
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`define REQQ_SIZE `NT*`NW
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// Miss Reserv Queue Knob
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`define MRVQ_SIZE `REQQ_SIZE
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// Dram Fill Rsp Queue Size
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`define DFPQ_SIZE 2
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// Queues for writebacks Knobs
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// Core Writeback Queue Size
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`define CWBQ_SIZE `REQQ_SIZE
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// Dram Writeback Queue Size
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`define DWBQ_SIZE 2
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// Dram Fill Req Queue Size
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`define DFQQ_SIZE `REQQ_SIZE
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// Dram knobs
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`define SIMULATED_DRAM_LATENCY_CYCLES 50
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// ========================================= Configurable Knobs =========================================
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`define vx_clog2_h(value, x) (value == (1 << x)) ? (x)
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`define vx_clog2(value) (value == 0 ) ? 0 : \
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(value == 1 ) ? 1 : \
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`vx_clog2_h(value, 2 ) : \
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`vx_clog2_h(value, 3 ) : \
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`vx_clog2_h(value, 4 ) : \
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`vx_clog2_h(value, 5 ) : \
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`vx_clog2_h(value, 6 ) : \
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`vx_clog2_h(value, 7 ) : \
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`vx_clog2_h(value, 8 ) : \
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`vx_clog2_h(value, 9 ) : \
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`vx_clog2_h(value, 10) : \
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`vx_clog2_h(value, 11) : \
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`vx_clog2_h(value, 12) : \
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`vx_clog2_h(value, 13) : \
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`vx_clog2_h(value, 14) : \
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`vx_clog2_h(value, 15) : \
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`vx_clog2_h(value, 16) : \
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`vx_clog2_h(value, 17) : \
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`vx_clog2_h(value, 18) : \
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`vx_clog2_h(value, 19) : \
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`vx_clog2_h(value, 20) : \
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`vx_clog2_h(value, 21) : \
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`vx_clog2_h(value, 22) : \
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`vx_clog2_h(value, 23) : \
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`vx_clog2_h(value, 24) : \
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`vx_clog2_h(value, 25) : \
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`vx_clog2_h(value, 26) : \
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`vx_clog2_h(value, 27) : \
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`vx_clog2_h(value, 28) : \
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`vx_clog2_h(value, 29) : \
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`vx_clog2_h(value, 30) : \
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`vx_clog2_h(value, 31) : \
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0
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`define BANK_SIZE_BYTES `CACHE_SIZE_BYTES/`NUMBER_BANKS
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`define BANK_LINE_COUNT `BANK_SIZE_BYTES/`BANK_LINE_SIZE_BYTES
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`define BANK_LINE_SIZE_WORDS `BANK_LINE_SIZE_BYTES / `WORD_SIZE_BYTES
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`define BANK_LINE_SIZE_RNG `BANK_LINE_SIZE_WORDS-1:0
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// Offset is fixed
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`define OFFSET_SIZE_END 1
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`define OFFSET_ADDR_START 0
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`define OFFSET_ADDR_END 1
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`define OFFSET_ADDR_RNG `OFFSET_ADDR_START:`OFFSET_ADDR_END
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`define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0
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`define WORD_SELECT_NUM_BITS `vx_clog2(`BANK_LINE_SIZE_WORDS)
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`define WORD_SELECT_SIZE_END `WORD_SELECT_NUM_BITS
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`define WORD_SELECT_ADDR_START 1+`OFFSET_ADDR_END
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`define WORD_SELECT_ADDR_END `WORD_SELECT_SIZE_END+`OFFSET_ADDR_END
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`define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START
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`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:WORD_SELECT_SIZE_END
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`define BANK_SELECT_NUM_BITS `vx_clog2(`NUMBER_BANKS)
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`define BANK_SELECT_SIZE_END `BANK_SELECT_NUM_BITS
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`define BANK_SELECT_ADDR_START 1+`WORD_SELECT_ADDR_END
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`define BANK_SELECT_ADDR_END `BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START
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`define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START
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`define BANK_SELECT_SIZE_RNG `BANK_SELECT_SIZE_END-1:0
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`define LINE_SELECT_NUM_BITS `vx_clog2(`BANK_LINE_COUNT)
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`define LINE_SELECT_SIZE_END `LINE_SELECT_NUM_BITS
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`define LINE_SELECT_ADDR_START 1+`BANK_SELECT_ADDR_END
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`define LINE_SELECT_ADDR_END `LINE_SELECT_SIZE_END+`LINE_SELECT_ADDR_START
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`define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START
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`define LINE_SELECT_SIZE_RNG `LINE_SELECT_SIZE_END-1:0
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`define TAG_SELECT_NUM_BITS 32-`LINE_SELECT_ADDR_RNG+1
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`define TAG_SELECT_SIZE_END `TAG_SELECT_NUM_BITS
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`define TAG_SELECT_ADDR_START 1+`LINE_SELECT_ADDR_RNG
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`define TAG_SELECT_ADDR_END `TAG_SELECT_SIZE_END+`TAG_SELECT_ADDR_START
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`define TAG_SELECT_ADDR_RNG `TAG_SELECT_ADDR_END:`TAG_SELECT_ADDR_START
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`define TAG_SELECT_SIZE_RNG `TAG_SELECT_SIZE_END-1:0
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