214 lines
7.2 KiB
Verilog
214 lines
7.2 KiB
Verilog
`include "VX_tex_define.vh"
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module VX_tex_memory #(
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parameter CORE_ID = 0,
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parameter REQ_INFO_WIDTH = 1
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) (
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input wire clk,
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input wire reset,
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// memory interface
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VX_dcache_core_req_if dcache_req_if,
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VX_dcache_core_rsp_if dcache_rsp_if,
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// inputs
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input wire req_valid,
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input wire [`NW_BITS-1:0] req_wid,
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input wire [`NUM_THREADS-1:0] req_tmask,
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input wire [31:0] req_PC,
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input wire [`TEX_FILTER_BITS-1:0] req_filter,
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input wire [`TEX_STRIDE_BITS-1:0] req_stride,
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input wire [`NUM_THREADS-1:0][3:0][31:0] req_addr,
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input wire [REQ_INFO_WIDTH-1:0] req_info,
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output wire req_ready,
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// outputs
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output wire rsp_valid,
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output wire [`NW_BITS-1:0] rsp_wid,
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output wire [`NUM_THREADS-1:0] rsp_tmask,
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output wire [31:0] rsp_PC,
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output wire [`TEX_FILTER_BITS-1:0] rsp_filter,
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output wire [`NUM_THREADS-1:0][3:0][31:0] rsp_data,
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output wire [REQ_INFO_WIDTH-1:0] rsp_info,
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input wire rsp_ready
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);
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`UNUSED_PARAM (CORE_ID)
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wire [3:0] dup_reqs;
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wire [3:0][`NUM_THREADS-1:0][29:0] req_addr_w;
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wire [3:0][`NUM_THREADS-1:0][1:0] align_offs;
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// reorder address into quads
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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for (genvar j = 0; j < 4; ++j) begin
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assign req_addr_w[j][i] = req_addr[i][j][31:2];
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assign align_offs[j][i] = req_addr[i][j][1:0];
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end
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end
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// find duplicate addresses
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for (genvar i = 0; i < 4; ++i) begin
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wire [`NUM_THREADS-1:0] addr_matches;
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for (genvar j = 0; j < `NUM_THREADS; j++) begin
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assign addr_matches[j] = (req_addr_w[i][0] == req_addr_w[i][j]) || ~req_tmask[j];
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end
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assign dup_reqs[i] = req_tmask[0] && (& addr_matches);
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end
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// save requet metadata into index buffer
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wire [`LSUQ_ADDR_BITS-1:0] mbuf_waddr, mbuf_raddr;
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wire mbuf_push, mbuf_pop, mbuf_full;
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wire [REQ_INFO_WIDTH-1:0] ib_req_info;
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wire [`TEX_FILTER_BITS-1:0] ib_req_filter;
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wire [`TEX_STRIDE_BITS-1:0] ib_stride;
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wire [3:0][`NUM_THREADS-1:0][1:0] ib_align_offs;
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wire [3:0] ib_dup_reqs;
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assign mbuf_push = req_valid && req_ready;
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VX_index_buffer #(
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.DATAW (REQ_INFO_WIDTH + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (4 * `NUM_THREADS * 2) + 4),
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.SIZE (`LSUQ_SIZE)
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) req_metadata (
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.clk (clk),
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.reset (reset),
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.write_addr (mbuf_waddr),
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.acquire_slot (mbuf_push),
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.read_addr (mbuf_raddr),
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.write_data ({req_info, req_filter, req_stride, align_offs, dup_reqs}),
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.read_data ({ib_req_info, ib_req_filter, ib_stride, ib_align_offs, ib_dup_reqs}),
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.release_addr (mbuf_raddr),
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.release_slot (mbuf_pop),
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.full (mbuf_full)
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);
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// can take more requests?
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assign req_ready = ~mbuf_full;
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// save request addresses into fifo
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wire reqq_empty, reqq_full;
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wire reqq_push, reqq_pop;
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wire [3:0][`NUM_THREADS-1:0][29:0] q_req_addr;
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wire [`LSUQ_ADDR_BITS-1:0] q_ib_waddr;
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wire [`NW_BITS-1:0] q_req_wid;
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wire [`NUM_THREADS-1:0] q_req_tmask;
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wire [31:0] q_req_PC;
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wire [`TEX_FILTER_BITS-1:0] q_req_filter;
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wire [3:0] q_dup_reqs;
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assign reqq_push = mbuf_push;
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VX_fifo_queue #(
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.DATAW (`NUM_THREADS * 4 * 30 + `LSUQ_ADDR_BITS + `NW_BITS + `NUM_THREADS + 32 + `TEX_FILTER_BITS + 4),
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.SIZE (`LSUQ_SIZE),
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.BUFFERED (1)
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) req_queue (
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.clk (clk),
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.reset (reset),
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.push (reqq_push),
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.pop (reqq_pop),
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.data_in ({req_addr_w, mbuf_waddr, req_wid, req_tmask, req_PC, req_filter, dup_reqs}),
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.data_out ({q_req_addr, q_ib_waddr, q_req_wid, q_req_tmask, q_req_PC, q_req_filter, q_dup_reqs}),
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.empty (reqq_empty),
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`UNUSED_PIN (full),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (size)
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);
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///////////////////////////////////////////////////////////////////////////
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wire [`NUM_THREADS-1:0][29:0] texel_addr;
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wire texel_valid, texel_sent, last_texel_sent;
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wire texel_is_dup;
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reg [1:0] texel_idx;
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always @(posedge clk) begin
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if (reset || last_texel_sent) begin
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texel_idx <= 0;
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end else if (texel_sent) begin
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texel_idx <= texel_idx + 1;
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end
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end
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assign texel_valid = ~reqq_empty;
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assign texel_addr = q_req_addr[texel_idx];
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assign texel_is_dup = q_dup_reqs[texel_idx];
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wire is_last_texel = (texel_idx == (q_req_filter ? 3 : 0));
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assign last_texel_sent = texel_sent && is_last_texel;
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assign reqq_pop = last_texel_sent;
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// DCache Request
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reg [`NUM_THREADS-1:0] texel_sent_mask;
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wire [`NUM_THREADS-1:0] dcache_req_fire;
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assign dcache_req_fire = dcache_req_if.valid & dcache_req_if.ready;
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assign texel_sent = (&(dcache_req_fire | texel_sent_mask | ~q_req_tmask))
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|| (texel_is_dup & dcache_req_if.valid[0] & dcache_req_if.ready[0]);
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always @(posedge clk) begin
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if (reset) begin
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texel_sent_mask <= 0;
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end else begin
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if (texel_sent)
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texel_sent_mask <= 0;
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else
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texel_sent_mask <= texel_sent_mask | (dcache_req_if.valid & dcache_req_if.ready);
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end
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end
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wire [`NUM_THREADS-1:0] dup_mask = {{(`NUM_THREADS-1){~texel_is_dup}}, 1'b1};
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assign dcache_req_if.valid = {`NUM_THREADS{texel_valid}} & q_req_tmask & dup_mask & ~texel_sent_mask;
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assign dcache_req_if.rw = {`NUM_THREADS{1'b0}};
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assign dcache_req_if.addr = texel_addr;
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assign dcache_req_if.byteen = {`NUM_THREADS{4'b1111}};
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assign dcache_req_if.data = 'x;
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`ifdef DBG_CACHE_REQ_INFO
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assign dcache_req_if.tag = {`NUM_THREADS{q_req_PC, q_req_wid, texel_idx, q_ib_waddr}};
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`else
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assign dcache_req_if.tag = {`NUM_THREADS{q_ib_waddr}};
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`endif
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// Dcache Response
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reg [3:0][`NUM_THREADS-1:0][31:0] rsp_texels;
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reg [`LSUQ_SIZE-1:0][3:0][`NUM_THREADS-1:0] rsp_rem_mask;
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wire dcache_rsp_fire;
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wire [1:0] rsp_texel_idx;
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wire rsp_is_dup;
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assign dcache_rsp_fire = (| dcache_rsp_if.valid) && dcache_rsp_if.ready;
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wire [`NUM_THREADS-1:0] rsp_rem_mask_n = rsp_rem_mask[mbuf_raddr][rsp_texel_idx] & ~dcache_rsp_if.valid;
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always @(posedge clk) begin
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if ((|dcache_req_fire) && (0 == texel_sent_mask)) begin
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rsp_rem_mask[q_ib_waddr][rsp_texel_idx] <= q_req_tmask;
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end
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if (dcache_rsp_fire) begin
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rsp_rem_mask[mbuf_raddr][rsp_texel_idx] <= rsp_rem_mask_n;
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end
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end
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assign mbuf_raddr = dcache_rsp_if.tag[`LSUQ_ADDR_BITS-1:0];
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assign rsp_texel_idx = dcache_rsp_if.tag[`LSUQ_ADDR_BITS-1+:2];
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assign rsp_is_dup = ib_dup_reqs[rsp_texel_idx];
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assign rsp_tmask = rsp_is_dup ? rsp_rem_mask[mbuf_raddr][rsp_texel_idx]: dcache_rsp_if.valid;
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assign mbuf_pop = dcache_rsp_fire && (0 == rsp_rem_mask_n || rsp_is_dup);
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endmodule
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