50 lines
1.1 KiB
Verilog
50 lines
1.1 KiB
Verilog
`include "VX_define.vh"
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module VX_shift_register #(
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parameter DATAW = 1,
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parameter DEPTH = 0
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) (
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input wire clk,
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input wire reset,
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input wire enable,
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input wire [DATAW-1:0] in,
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output wire [DATAW-1:0] out
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);
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if (0 == DEPTH) begin
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assign out = in;
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end if (1 == DEPTH) begin
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reg [DATAW-1:0] ram;
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always @(posedge clk) begin
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if (reset) begin
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ram <= '0;
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end else begin
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if (enable) begin
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ram <= in;
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end
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end
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end
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assign out = ram;
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end else begin
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reg [DEPTH-1:0][DATAW-1:0] ram;
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always @(posedge clk) begin
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if (reset) begin
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ram <= '0;
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end else begin
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if (enable) begin
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ram <= {ram[DEPTH-2:0], in};
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end
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end
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end
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assign out = ram [DEPTH-1];
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end
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endmodule |