16 lines
381 B
Verilog
16 lines
381 B
Verilog
`ifndef VX_GPU_DRAM_DCACHE_RSP
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`define VX_GPU_DRAM_DCACHE_RSP
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`include "../cache/VX_cache_config.vh"
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interface VX_gpu_dcache_dram_rsp_if #(
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parameter BANK_LINE_WORDS = 2
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) ();
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// DRAM Response
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wire dram_rsp_valid;
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wire [31:0] dram_rsp_addr;
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wire [BANK_LINE_WORDS-1:0][31:0] dram_rsp_data;
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endinterface
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`endif |