124 lines
4.2 KiB
Verilog
124 lines
4.2 KiB
Verilog
`include "VX_platform.vh"
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module VX_serial_div #(
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parameter WIDTHN = 1,
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parameter WIDTHD = 1,
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parameter WIDTHQ = 1,
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parameter WIDTHR = 1,
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parameter LANES = 1,
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parameter TAGW = 1
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [LANES-1:0][WIDTHN-1:0] numer,
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input wire [LANES-1:0][WIDTHD-1:0] denom,
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input wire signed_mode,
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input wire [TAGW-1:0] tag_in,
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output wire [LANES-1:0][WIDTHQ-1:0] quotient,
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output wire [LANES-1:0][WIDTHR-1:0] remainder,
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input wire ready_out,
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output wire valid_out,
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output wire [TAGW-1:0] tag_out
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);
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localparam MIN_ND = (WIDTHN < WIDTHD) ? WIDTHN : WIDTHD;
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localparam CNTRW = $clog2(WIDTHN+1);
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reg [LANES-1:0][WIDTHN + MIN_ND:0] working;
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reg [LANES-1:0][WIDTHD-1:0] denom_r;
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wire [LANES-1:0][WIDTHN-1:0] numer_qual;
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wire [LANES-1:0][WIDTHD-1:0] denom_qual;
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wire [LANES-1:0][WIDTHD:0] sub_result;
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reg [LANES-1:0] inv_quot, inv_rem;
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reg [CNTRW-1:0] cntr;
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reg is_busy;
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reg [TAGW-1:0] tag_r;
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wire done = ~(| cntr);
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wire push = valid_in && ready_in;
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wire pop = valid_out && ready_out;
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for (genvar i = 0; i < LANES; ++i) begin
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wire negate_numer = signed_mode && numer[i][WIDTHN-1];
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wire negate_denom = signed_mode && denom[i][WIDTHD-1];
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assign numer_qual[i] = (numer[i] ^ {WIDTHN{negate_numer}}) + WIDTHN'(negate_numer);
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assign denom_qual[i] = (denom[i] ^ {WIDTHD{negate_denom}}) + WIDTHD'(negate_denom);
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assign sub_result[i] = working[i][WIDTHN + MIN_ND : WIDTHN] - denom_r[i];
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end
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always @(posedge clk) begin
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if (reset) begin
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cntr <= 0;
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is_busy <= 0;
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end
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else begin
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if (push) begin
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for (integer i = 0; i < LANES; ++i) begin
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working[i] <= {{WIDTHD{1'b0}}, numer_qual[i], 1'b0};
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denom_r[i] <= denom_qual[i];
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inv_quot[i] <= (denom[i] != 0) && signed_mode && (numer[i][31] ^ denom[i][31]);
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inv_rem[i] <= signed_mode && numer[i][31];
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end
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tag_r <= tag_in;
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cntr <= WIDTHN;
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is_busy <= 1;
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end
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else begin
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if (!done) begin
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for (integer i = 0; i < LANES; ++i) begin
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working[i] <= sub_result[i][WIDTHD] ? {working[i][WIDTHN+MIN_ND-1:0], 1'b0} :
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{sub_result[i][WIDTHD-1:0], working[i][WIDTHN-1:0], 1'b1};
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end
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cntr <= cntr - CNTRW'(1);
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end
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end
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if (pop) begin
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is_busy <= 0;
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end
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end
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end
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for (genvar i = 0; i < LANES; ++i) begin
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assign quotient[i] = (working[i][WIDTHQ-1:0] ^ {WIDTHQ{inv_quot[i]}}) + WIDTHQ'(inv_quot[i]);
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assign remainder[i] = (working[i][WIDTHN+WIDTHR:WIDTHN+1] ^ {WIDTHR{inv_rem[i]}}) + WIDTHR'(inv_rem[i]);
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end
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assign ready_in = !is_busy;
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assign tag_out = tag_r;
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assign valid_out = is_busy && done;
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/*reg [LANES-1:0][WIDTHQ-1:0] quotient_r;
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reg [LANES-1:0][WIDTHR-1:0] remainder_r;
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reg [TAGW-1:0] tag_out_r;
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reg valid_out_r;
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wire stall_out = !ready_out && valid_out_r;
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assign pop = is_busy && done && !stall_out;
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always @(posedge clk) begin
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if (reset) begin
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valid_out_r <= 0;
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end else if (~stall_out) begin
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for (integer i = 0; i < LANES; ++i) begin
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quotient_r[i] <= (working[i][WIDTHQ-1:0] ^ {WIDTHQ{inv_quot[i]}}) + WIDTHQ'(inv_quot[i]);
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remainder_r[i] <= ((working[i][WIDTHN+WIDTHR-1:WIDTHN] >> 1) ^ {WIDTHR{inv_rem[i]}}) + WIDTHR'(inv_rem[i]);
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end
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tag_out_r <= tag_r;
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valid_out_r <= is_busy && done;
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end
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end
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assign ready_in = !is_busy;
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assign quotient = quotient_r;
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assign remainder = remainder_r;
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assign tag_out = tag_out_r;
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assign valid_out = valid_out_r;*/
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endmodule |