Blaise Tine 4683def6dd timimg fixes

2021-04-04 07:59:43 -07:00

..

cache

lkg build rollout with 16cores optimization on arria10

2021-01-24 16:49:22 -08:00

core

synthesis makefile update

2021-04-04 04:03:22 -07:00

pipeline

fpga build fixes

2021-04-02 23:34:58 -07:00

top1

synthesis makefile update

2021-04-04 04:03:22 -07:00

top2

synthesis makefile update

2021-04-04 04:03:22 -07:00

top4

synthesis makefile update

2021-04-04 04:03:22 -07:00

top8

synthesis makefile update

2021-04-04 04:03:22 -07:00

top16

synthesis makefile update

2021-04-04 04:03:22 -07:00

top32

synthesis makefile update

2021-04-04 04:03:22 -07:00

top64

synthesis makefile update

2021-04-04 04:03:22 -07:00

unittest

minor updates

2021-01-06 07:18:14 -08:00

vortex

synthesis makefile update

2021-04-04 04:03:22 -07:00

.gitignore

minor update

2021-02-21 15:14:46 -08:00

Makefile

minor update

2021-04-02 14:15:58 -07:00

project.sdc

minor update

2021-02-15 09:23:40 -08:00

project.tcl

timimg fixes

2021-04-04 07:59:43 -07:00

timing-html.tcl

performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00