654 lines
20 KiB
Systemverilog
654 lines
20 KiB
Systemverilog
//
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// Copyright (c) 2017, Intel Corporation
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// Neither the name of the Intel Corporation nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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// Read from the memory locations first and then write to the memory locations
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`include "platform_if.vh"
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`include "afu_json_info.vh"
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module ccip_std_afu
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(
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// CCI-P Clocks and Resets
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input logic pClk, // 400MHz - CCI-P clock domain. Primary interface clock
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input logic pClkDiv2, // 200MHz - CCI-P clock domain.
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input logic pClkDiv4, // 100MHz - CCI-P clock domain.
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input logic uClk_usr, // User clock domain. Refer to clock programming guide ** Currently provides fixed 300MHz clock **
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input logic uClk_usrDiv2, // User clock domain. Half the programmed frequency ** Currently provides fixed 150MHz clock **
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input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset
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input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State
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input logic pck_cp2af_error, // CCI-P Protocol Error Detected
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// Interface structures
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input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port
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output t_if_ccip_Tx pck_af2cp_sTx // CCI-P Tx Port
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);
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//
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// Run the entire design at the standard CCI-P frequency (400 MHz).
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//
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logic clk;
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assign clk = pClk;
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logic reset;
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assign reset = pck_cp2af_softReset;
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logic [511:0] wr_data;
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logic [511:0] rd_data;
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logic do_update;
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logic start_read;
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logic start_write;
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logic wr_addr_next_valid;
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logic addr_next_valid;
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logic rd_end_of_list;
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logic rd_needed;
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logic wr_needed;
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logic read_req;
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logic write_req;
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logic [15:0] cnt_list_length;
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t_ccip_clAddr rd_addr;
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t_ccip_clAddr wr_addr;
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t_ccip_clAddr addr_next;
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t_ccip_clAddr wr_addr_next;
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// =========================================================================
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//
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// Register requests.
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//
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// =========================================================================
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//
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// The incoming pck_cp2af_sRx and outgoing pck_af2cp_sTx must both be
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// registered. Here we register pck_cp2af_sRx and assign it to sRx.
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// We also assign pck_af2cp_sTx to sTx here but don't register it.
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// The code below never uses combinational logic to write sTx.
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//
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t_if_ccip_Rx sRx;
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always_ff @(posedge clk)
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begin
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sRx <= pck_cp2af_sRx;
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end
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t_if_ccip_Tx sTx;
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assign pck_af2cp_sTx = sTx;
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// =========================================================================
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//
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// CSR (MMIO) handling.
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//
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// =========================================================================
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// The AFU ID is a unique ID for a given program. Here we generated
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// one with the "uuidgen" program and stored it in the AFU's JSON file.
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// ASE and synthesis setup scripts automatically invoke afu_json_mgr
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// to extract the UUID into afu_json_info.vh.
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logic [127:0] afu_id = `AFU_ACCEL_UUID;
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//
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// A valid AFU must implement a device feature list, starting at MMIO
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// address 0. Every entry in the feature list begins with 5 64-bit
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// words: a device feature header, two AFU UUID words and two reserved
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// words.
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//
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// Is a CSR read request active this cycle?
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logic is_csr_read;
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assign is_csr_read = sRx.c0.mmioRdValid;
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// Is a CSR write request active this cycle?
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logic is_csr_write;
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assign is_csr_write = sRx.c0.mmioWrValid;
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// The MMIO request header is overlayed on the normal c0 memory read
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// response data structure. Cast the c0Rx header to an MMIO request
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// header.
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t_ccip_c0_ReqMmioHdr mmio_req_hdr;
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assign mmio_req_hdr = t_ccip_c0_ReqMmioHdr'(sRx.c0.hdr);
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//
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// Implement the device feature list by responding to MMIO reads.
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//
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always_ff @(posedge clk)
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begin
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if (reset)
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begin
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sTx.c2.mmioRdValid <= 1'b0;
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end
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else
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begin
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// Always respond with something for every read request
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sTx.c2.mmioRdValid <= is_csr_read;
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// The unique transaction ID matches responses to requests
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sTx.c2.hdr.tid <= mmio_req_hdr.tid;
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// Addresses are of 32-bit objects in MMIO space. Addresses
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// of 64-bit objects are thus multiples of 2.
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case (mmio_req_hdr.address)
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0: // AFU DFH (device feature header)
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begin
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// Here we define a trivial feature list. In this
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// example, our AFU is the only entry in this list.
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sTx.c2.data <= t_ccip_mmioData'(0);
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// Feature type is AFU
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sTx.c2.data[63:60] <= 4'h1;
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// End of list (last entry in list)
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sTx.c2.data[40] <= 1'b1;
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end
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// AFU_ID_L
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2: sTx.c2.data <= afu_id[63:0];
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// AFU_ID_H
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4: sTx.c2.data <= afu_id[127:64];
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// DFH_RSVD0
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6: sTx.c2.data <= t_ccip_mmioData'(0);
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// DFH_RSVD1
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8: sTx.c2.data <= t_ccip_mmioData'(0);
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// Updated by apurve to check fpgaReadMMIO
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10: sTx.c2.data <= t_ccip_mmioData'(start_read);
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default: sTx.c2.data <= t_ccip_mmioData'(0);
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endcase
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end
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end
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//
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// CSR write handling. Host software must tell the AFU the memory address
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// to which it should be writing. The address is set by writing a CSR.
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//
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// We use MMIO address 0 to set the memory address. The read and
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// write MMIO spaces are logically separate so we are free to use
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// whatever we like. This may not be good practice for cleanly
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// organizing the MMIO address space, but it is legal.
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logic is_mem_addr_csr_write;
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assign is_mem_addr_csr_write = is_csr_write &&
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(mmio_req_hdr.address == t_ccip_mmioAddr'(0));
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// Memory address to which this AFU will write.
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t_ccip_clAddr write_mem_addr;
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always_ff @(posedge clk)
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begin
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if (reset)
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begin
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start_write <= 1'b0;
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end
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else if (is_mem_addr_csr_write)
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begin
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write_mem_addr <= t_ccip_clAddr'(sRx.c0.data);
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start_write <= 1'b1;
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//$display("Write mem address is 0x%x", t_ccip_clAddr'(write_mem_addr));
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end
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end
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// We use MMIO address 8 to set the memory address for reading data.
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logic is_mem_addr_csr_read;
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assign is_mem_addr_csr_read = is_csr_write &&
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(mmio_req_hdr.address == t_ccip_mmioAddr'(2));
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// Memory address from which this AFU will read.
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t_ccip_clAddr read_mem_addr;
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//logic start_traversal = 'b0;
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//t_ccip_clAddr start_traversal_addr;
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always_ff @(posedge clk)
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begin
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if (reset)
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begin
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start_read <= 1'b0;
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end
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else if (is_mem_addr_csr_read)
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begin
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read_mem_addr <= t_ccip_clAddr'(sRx.c0.data);
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start_read <= 1'b1;
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//$display("Read mem address is 0x%x", t_ccip_clAddr'(read_mem_addr));
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end
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end
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// =========================================================================
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//
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// Main AFU logic
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//
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// =========================================================================
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//
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// States in our simple example.
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//
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//typedef enum logic [0:0]
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typedef enum logic [1:0]
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{
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STATE_IDLE,
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STATE_READ,
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STATE_UPDATE,
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STATE_WRITE
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}
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t_state;
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t_state state;
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//
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// State machine
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//
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always_ff @(posedge clk)
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begin
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if (reset)
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begin
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state <= STATE_IDLE;
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rd_end_of_list <= 1'b0;
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end
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else
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begin
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case (state)
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STATE_IDLE:
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begin
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// Traversal begins when CSR 1 is written
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if (start_read)
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begin
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state <= STATE_READ;
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$display("AFU starting traversal at 0x%x", t_ccip_clAddr'(read_mem_addr));
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end
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end
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STATE_READ:
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begin
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$display("AFU in READ...");
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$display("do_update is %d...",do_update);
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$display("addr_next_valid is %d...",addr_next_valid);
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$display("rd_needed is %d...",rd_needed);
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if (!rd_needed && do_update)
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begin
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state <= STATE_UPDATE;
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$display("AFU moving to UPDATE...");
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end
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end
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STATE_UPDATE:
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begin
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// Update the read value to be written back
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$display("AFU in UPDATE...");
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if (!do_update)
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begin
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state <= STATE_WRITE;
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wr_needed <= 1'b1;
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$display("AFU moving to WRITE...");
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end
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end
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STATE_WRITE:
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begin
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// Write the updated value to the address
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// Point to new address after that
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// if done then point to IDLE; else read new values
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$display("AFU in WRITE...");
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if (rd_end_of_list)
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begin
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state <= STATE_IDLE;
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$display("AFU done...");
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end
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else if (!wr_needed)
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begin
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state <= STATE_READ;
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$display("AFU moving to READ from WRITE...");
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start_write <= 1'b0;
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write_req <= 1'b0;
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end
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end
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endcase
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end
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end
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// =========================================================================
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//
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// Read logic.
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//
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// =========================================================================
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//
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// READ REQUEST
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//
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// Did a write response just arrive
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// Next read address
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always_ff @(posedge clk)
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begin
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// Next read address is valid when we have got the write response back
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if (sRx.c1.rspValid)
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begin
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addr_next_valid <= sRx.c1.rspValid;
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//if (state == STATE_READ && !rd_needed)
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//begin
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// Apurve: Next address is current address plus address length
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//addr_next <= addr_next + addr_size;
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addr_next <= (addr_next_valid ? rd_addr + 0 : rd_addr);
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// End of list reached if we have read 5 times
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rd_end_of_list <= (cnt_list_length == 'h5);
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//end
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end
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end
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//
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// Since back pressure may prevent an immediate read request, we must
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// record whether a read is needed and hold it until the request can
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// be sent to the FIU.
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//
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always_ff @(posedge clk)
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begin
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if (reset)
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begin
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rd_needed <= 1'b0;
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end
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else
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begin
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// If reads are allowed this cycle then we can safely clear
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// any previously requested reads. This simple AFU has only
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// one read in flight at a time since it is walking a pointer
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// chain.
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if (rd_needed)
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begin
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//rd_needed <= sRx.c0TxAlmFull;
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//rd_needed <= (!sRx.c0TxAlmFull && !sRx.c0.rspValid);
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rd_needed <= !sRx.c0.rspValid;
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end
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else if (state == STATE_READ)
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begin
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// Need a read under two conditions:
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// - Starting a new walk
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// - A read response just arrived from a line containing
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// a next pointer.
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rd_needed <= (start_read || (!sRx.c0TxAlmFull && (addr_next_valid && ! rd_end_of_list)));
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rd_addr <= (start_read ? read_mem_addr : addr_next);
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//$display("rd_addr is 0x%x", t_ccip_clAddr'(rd_addr));
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//$display("read mem addr is 0x%x", t_ccip_clAddr'(read_mem_addr));
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//$display("start read is %d", start_read);
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end
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end
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end
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//
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// Emit read requests to the FIU.
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//
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// Read header defines the request to the FIU
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t_ccip_c0_ReqMemHdr rd_hdr;
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always_comb
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begin
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rd_hdr = t_ccip_c0_ReqMemHdr'(0);
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// Read request type (No intention to cache)
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//rd_hdr.req_type = 4'h0;
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// Virtual address (MPF virtual addressing is enabled)
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rd_hdr.address = rd_addr;
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// Read over channel VA
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//rd_hdr.vc_sel = 2'h0;
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// Read one cache line (64 bytes)
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//rd_hdr.cl_len = 2'h0;
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end
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// Send read requests to the FIU
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always_ff @(posedge clk)
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begin
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if (reset)
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begin
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sTx.c0.valid <= 1'b0;
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cnt_list_length <= 0;
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read_req <= 1'b0;
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end
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else
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begin
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// Generate a read request when needed and the FIU isn't full
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if (state == STATE_READ)
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begin
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sTx.c0.valid <= (rd_needed && !sRx.c0TxAlmFull && !read_req);
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if (rd_needed && !sRx.c0TxAlmFull && !read_req)
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begin
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sTx.c0.hdr <= rd_hdr;
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cnt_list_length <= cnt_list_length + 1;
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read_req <= 1'b1;
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$display("Incrementing read count...%d",cnt_list_length);
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$display("Read address is 0x%x...",rd_hdr.address);
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addr_next_valid <= 1'b0;
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// Apurve: Add something to stop read once this section has been accessed
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//rd_needed <= 1'b0;
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end
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end
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end
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end
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//
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// READ RESPONSE HANDLING
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//
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//
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// Receive data (read responses).
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//
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always_ff @(posedge clk)
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begin
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if (reset)
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begin
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do_update <= 1'b0;
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end
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else
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begin
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if (!do_update && sRx.c0.rspValid)
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begin
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rd_data <= sRx.c0.data;
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do_update <= 1'b1;
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$display("rd data is %d...",rd_data);
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end
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if ((state == STATE_UPDATE) && (do_update == 1'b1))
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begin
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// Update the read data and put it in the write data to be written
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wr_data <= rd_data + 2;
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do_update <= 1'b0;
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read_req <= 1'b0;
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$display("write data is %d...",wr_data);
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// First read done. Next reads should be from the updated addresses
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start_read <= 1'b0;
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end
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end
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end
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// =========================================================================
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//
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// Write logic.
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//
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// =========================================================================
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//
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// WRITE REQUEST
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//
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// Did a write response just arrive
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// Next write address
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always_ff @(posedge clk)
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begin
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if (sRx.c0.rspValid)
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begin
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// Next write address is valid when we have got the read response back
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wr_addr_next_valid <= sRx.c0.rspValid;
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//wr_addr_next_valid <= (!start_write && sRx.c0.rspValid);
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//if (state == STATE_WRITE && !wr_needed)
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//begin
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// Apurve: Next address is current address plus address length
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//wr_addr_next <= wr_addr + 0;
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wr_addr_next <= (wr_addr_next_valid ? wr_addr + 0 : wr_addr);
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//end
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end
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end
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//
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// Since back pressure may prevent an immediate write request, we must
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// record whether a write is needed and hold it until the request can
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// be sent to the FIU.
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//
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always_ff @(posedge clk)
|
|
begin
|
|
if (reset)
|
|
begin
|
|
wr_needed <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
// If writes are allowed this cycle then we can safely clear
|
|
// any previously requested writes. This simple AFU has only
|
|
// one write in flight at a time since it is walking a pointer
|
|
// chain.
|
|
if (wr_needed)
|
|
begin
|
|
//wr_needed <= sRx.c1TxAlmFull;
|
|
//wr_needed <= (!sRx.c1TxAlmFull && !sRx.c1.rspValid);
|
|
wr_needed <= !sRx.c1.rspValid;
|
|
end
|
|
else
|
|
begin
|
|
// Need a write under two conditions:
|
|
// - Starting a new walk
|
|
// - A write response just arrived from a line containing
|
|
// a next pointer.
|
|
wr_needed <= (start_write || (!sRx.c1TxAlmFull && wr_addr_next_valid));
|
|
wr_addr <= (start_write ? write_mem_addr : wr_addr_next);
|
|
//$display("Write mem address later is 0x%x", t_ccip_clAddr'(write_mem_addr));
|
|
end
|
|
end
|
|
end
|
|
|
|
//
|
|
// Emit write requests to the FIU.
|
|
//
|
|
|
|
// Write header defines the request to the FIU
|
|
t_ccip_c1_ReqMemHdr wr_hdr;
|
|
|
|
always_comb
|
|
begin
|
|
wr_hdr = t_ccip_c1_ReqMemHdr'(0);
|
|
|
|
// Write request type
|
|
//wr_hdr.req_type = 4'h0;
|
|
|
|
// Virtual address (MPF virtual addressing is enabled)
|
|
wr_hdr.address = wr_addr;
|
|
|
|
// Let the FIU pick the channel
|
|
//wr_hdr.vc_sel = 2'h2;
|
|
|
|
// Write 1 cache line (64 bytes)
|
|
//wr_hdr.cl_len = 2'h0;
|
|
|
|
// Start of packet is true (single line write)
|
|
wr_hdr.sop = 1'b1;
|
|
end
|
|
|
|
// Send write requests to the FIU
|
|
always_ff @(posedge clk)
|
|
begin
|
|
if (reset)
|
|
begin
|
|
sTx.c1.valid <= 1'b0;
|
|
write_req <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
// Generate a write request when needed and the FIU isn't full
|
|
if (state == STATE_WRITE)
|
|
begin
|
|
sTx.c1.valid <= (wr_needed && !sRx.c1TxAlmFull && !write_req);
|
|
if (wr_needed && !sRx.c1TxAlmFull && !write_req)
|
|
begin
|
|
sTx.c1.hdr <= wr_hdr;
|
|
sTx.c1.data <= t_ccip_clData'(wr_data);
|
|
write_req <= 1'b1;
|
|
wr_addr_next_valid <= 1'b0;
|
|
$display("Write address is 0x%x...", wr_hdr.address);
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
//
|
|
// WRITE RESPONSE HANDLING
|
|
//
|
|
|
|
// Apurve: Check if a signal is to be sent to read to start reading in case
|
|
// write response does not work
|
|
//
|
|
// Send data (write requests).
|
|
//
|
|
//always_ff @(posedge clk)
|
|
//begin
|
|
// if (state == STATE_WRITE)
|
|
// begin
|
|
// rd_data <= sRx.c0.data;
|
|
// end
|
|
// if (state == STATE_UPDATE)
|
|
// begin
|
|
// // Update the write data and put it in the write data to be written
|
|
// wr_data <= rd_data + 1;
|
|
// end
|
|
//end
|
|
|
|
endmodule
|