86 lines
2.9 KiB
Verilog
86 lines
2.9 KiB
Verilog
`include "VX_cache_config.v"
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module VX_dcache_llv_resp_bank_sel
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#(
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// Size of cache in bytes
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parameter CACHE_SIZE_BYTES = 1024,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE_BYTES = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUMBER_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE_BYTES = 4,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUMBER_REQUESTS = 2,
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// Number of cycles to complete stage 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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// Dram knobs
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parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
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)
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(
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output reg [NUMBER_BANKS-1:0] per_bank_llvq_pop,
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input wire[NUMBER_BANKS-1:0] per_bank_llvq_valid,
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input wire[NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr,
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input wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data,
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input wire[NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid,
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input wire llvq_pop,
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output reg[NUMBER_REQUESTS-1:0] llvq_valid,
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output reg[NUMBER_REQUESTS-1:0][31:0] llvq_res_addr,
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output reg[NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data
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);
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wire [(`vx_clog2(NUMBER_BANKS))-1:0] main_bank_index;
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wire found_bank;
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VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_bank(
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.valids(per_bank_llvq_valid),
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.index (main_bank_index),
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.found (found_bank)
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);
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always @(*) begin
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llvq_valid = 0;
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llvq_res_addr = 0;
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llvq_res_data = 0;
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per_bank_llvq_pop = 0;
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if (found_bank && llvq_pop) begin
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llvq_valid [per_bank_llvq_res_tid[main_bank_index]] = 1'b1;
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llvq_res_addr[per_bank_llvq_res_tid[main_bank_index]] = per_bank_llvq_res_addr[main_bank_index];
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llvq_res_data[per_bank_llvq_res_tid[main_bank_index]] = per_bank_llvq_res_data[main_bank_index];
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per_bank_llvq_pop[main_bank_index] = 1'b1;
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end
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end
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endmodule
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