122 lines
3.2 KiB
Verilog
122 lines
3.2 KiB
Verilog
module VX_shared_memory_block
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#(
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parameter SMB_SIZE = 4096, // Bytes
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parameter SMB_BYTES_PER_READ = 16,
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parameter SMB_WORDS_PER_READ = 4,
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parameter SMB_LOG_WORDS_PER_READ = 2,
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parameter SMB_HEIGHT = 128, // Bytes
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parameter BITS_PER_BANK = 3
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)
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(
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input wire clk, // Clock
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input wire reset,
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//input wire[6:0] addr,
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//input wire[3:0][31:0] wdata,
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//input wire[1:0] we,
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//input wire shm_write,
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//output wire[3:0][31:0] data_out
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input wire[$clog2(SMB_HEIGHT) - 1:0] addr,
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input wire[SMB_WORDS_PER_READ-1:0][31:0] wdata,
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input wire[SMB_LOG_WORDS_PER_READ-1:0] we,
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input wire shm_write,
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output wire[SMB_WORDS_PER_READ-1:0][31:0] data_out
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);
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`ifndef SYN
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reg[SMB_WORDS_PER_READ-1:0][3:0][7:0] shared_memory[SMB_HEIGHT-1:0];
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wire [$clog2(SMB_HEIGHT) - 1:0]reg_addr;
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//wire need_to_write = (|we);
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integer curr_ind;
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// initial begin
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// for (curr_ind = 0; curr_ind < SMB_HEIGHT; curr_ind = curr_ind + 1)
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// begin
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// shared_memory[curr_ind] = 0;
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// end
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// end
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always @(posedge clk, posedge reset) begin
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if (reset) begin
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//for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1)
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end else if(shm_write) begin
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if (we == 2'b00) shared_memory[reg_addr][0] <= wdata[0];
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if (we == 2'b01) shared_memory[reg_addr][1] <= wdata[1];
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if (we == 2'b10) shared_memory[reg_addr][2] <= wdata[2];
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if (we == 2'b11) shared_memory[reg_addr][3] <= wdata[3];
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end
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end
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assign reg_addr = addr;
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// always @(posedge clk)
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// reg_addr <= addr;
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assign data_out = shm_write ? 0 : shared_memory[reg_addr];
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`else
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wire cena = 0;
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wire cenb = !shm_write;
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wire[3:0][31:0] write_bit_mask;
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//assign write_bit_mask[0] = (we == 2'b00) ? {32{1'b1}} : {32{1'b0}};
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//assign write_bit_mask[1] = (we == 2'b01) ? {32{1'b1}} : {32{1'b0}};
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//assign write_bit_mask[2] = (we == 2'b10) ? {32{1'b1}} : {32{1'b0}};
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//assign write_bit_mask[3] = (we == 2'b11) ? {32{1'b1}} : {32{1'b0}};
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genvar curr_word;
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for (curr_word = 0; curr_word < SMB_WORDS_PER_READ; curr_word = curr_word + 1)
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begin
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assign write_bit_mask[curr_word] = (we == curr_word) ? 1 : {32{1'b0}};
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end
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// Using ASIC MEM
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/* verilator lint_off PINCONNECTEMPTY */
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rf2_128x128_wm1 first_ram (
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.CENYA(),
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.AYA(),
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.CENYB(),
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.WENYB(),
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.AYB(),
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.QA(data_out),
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.SOA(),
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.SOB(),
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.CLKA(clk),
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.CENA(cena),
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.AA(addr),
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.CLKB(clk),
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.CENB(cenb),
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.WENB(write_bit_mask),
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.AB(addr),
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.DB(wdata),
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.EMAA(3'b011),
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.EMASA(1'b0),
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.EMAB(3'b011),
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.TENA(1'b1),
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.TCENA(1'b0),
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.TAA(7'b0),
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.TENB(1'b1),
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.TCENB(1'b0),
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.TWENB(128'b0),
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.TAB(7'b0),
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.TDB(128'b0),
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.RET1N(1'b1),
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.SIA(2'b0),
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.SEA(1'b0),
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.DFTRAMBYP(1'b0),
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.SIB(2'b0),
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.SEB(1'b0),
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.COLLDISN(1'b1)
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);
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/* verilator lint_on PINCONNECTEMPTY */
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`endif
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endmodule
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