Blaise Tine e770824d47 fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance

2021-01-10 20:26:15 -08:00

..

configs

project directories reorganization

2020-04-14 06:35:20 -04:00

dpi

speeding up simulation using dedicated full dpi-based FPU core

2021-01-06 18:44:06 -08:00

models/memory

RTL code refactoring

2020-04-19 03:38:00 -04:00

modelsim

yosys synthesis refactoring

2020-07-10 18:56:41 -04:00

old_rtl

refactoring fixes

2020-04-14 19:39:59 -04:00

opae

minor update

2021-01-06 23:30:30 -08:00

rtl

fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance

2021-01-10 20:26:15 -08:00

scripts

cache pipeline optimization - moved tag access to stage0

2021-01-03 23:10:41 -05:00

simulate

minor update

2021-01-07 00:18:10 -08:00

syn

fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance

2021-01-10 20:26:15 -08:00

unit_tests

scratchpad optimization for stack access using custom bank offset aligned to stack size

2021-01-02 16:00:00 -05:00

.gitignore

adding dram writeenable support + scheduler bug fixes

2020-05-27 19:00:23 -04:00

Makefile

scope refactoring

2020-10-03 18:53:21 -04:00