kernels/kernels/wu_arch_cases/README.md

Wu Architecture Staged Cases

This directory contains small bare-metal kernels for incremental Wu architecture testing. The original kernels/wu_arch kernel is useful as an integrated test, but it combines scalar spawning, tensor spawning, barriers, tensor control, and memory behavior in one large workload. These cases isolate those surfaces so failures can be reproduced faster under Verilator.

Case List

• case00_boot_scalar: minimal scalar boot, status writes, and pass marker.
• case01_scalar_spawn: scalar warp spawning without tensor warps or barriers.
• case02_tensor_spawn_stop: tensor warp spawn, marker store, and stop.
• case03_dual_fetch_issue: scalar and tensor warps active together to exercise split scheduling and issue.
• case04_scalar_barrier: scalar-domain barrier release.
• case05_tensor_barrier: tensor-domain barrier through tensor control.
• case06_masked_barrier: explicit mixed BAR_MASK with scalar warp 0 and tensor warps.
• case07_tensor_csr_tmc: tensor CSR/TMC path without barrier behavior.
• case08_tensor_lsu_optional: tensor LSU store/load marker path; keep last because memory interaction is broader and slower.

Each case has its own README.md describing the test objective, RTL surface, and expected pass marker.

Build

Use the suite Makefile from this directory:

make smoke -j4 LLVM_VORTEX=/home/hexu/dse/wu/virgo-artifact-full/toolchain/llvm-vortex2 RISCV_TOOLCHAIN_PATH=/home/hexu/dse/wu/virgo-artifact-full/chipyard/.conda-env/riscv-tools RISCV_PREFIX=riscv64-unknown-elf
make barriers -j4 LLVM_VORTEX=/home/hexu/dse/wu/virgo-artifact-full/toolchain/llvm-vortex2 RISCV_TOOLCHAIN_PATH=/home/hexu/dse/wu/virgo-artifact-full/chipyard/.conda-env/riscv-tools RISCV_PREFIX=riscv64-unknown-elf
make full -j4 LLVM_VORTEX=/home/hexu/dse/wu/virgo-artifact-full/toolchain/llvm-vortex2 RISCV_TOOLCHAIN_PATH=/home/hexu/dse/wu/virgo-artifact-full/chipyard/.conda-env/riscv-tools RISCV_PREFIX=riscv64-unknown-elf

smoke builds the boot/spawn/dual-issue cases. barriers builds the barrier-focused cases. full builds all cases.

Verilator Run Notes

For RTL simulation, use the same simulator setup as the main Virgo artifact, but run these ELFs one at a time:

• VM_PARALLEL_BUILDS=1
• LOADMEM=1, so SimDRAM::memory_init() preloads the ELF instead of relying on slow runtime SimTSI writes.
• CCACHE_DIR=/tmp/ccache when ccache is enabled in the sandbox.
• Use /home/hexu/dse/firtool-1.62.0 for firtool and /usr/local/bin/verilator for Verilator.
• Keep system gcc/g++ on PATH; do not use the gcc/g++ injected by chipyard/env.sh.
• For generated Verilator C++ compilation, prefer -O0 -fno-inline to reduce compile time.

Cleanup

make clean-all

This removes kernel ELF/dump outputs and the generated placeholder input blobs in each case directory.