122 lines
3.7 KiB
Verilog
122 lines
3.7 KiB
Verilog
`include "VX_define.vh"
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module VX_divide #(
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parameter WIDTHN=1,
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parameter WIDTHD=1,
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parameter NREP="UNSIGNED",
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parameter DREP="UNSIGNED",
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parameter SPEED="MIXED", // "MIXED" or "HIGHEST"
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parameter PIPELINE=0
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) (
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input clock, aclr, clken,
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input [WIDTHN-1:0] numer,
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input [WIDTHD-1:0] denom,
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output reg [WIDTHN-1:0] quotient,
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output reg [WIDTHD-1:0] remainder
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);
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generate
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if (NREP != DREP) begin
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different_nrep_drep_not_yet_supported non_existing_module();
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end
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`ifdef QUARTUS
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localparam lpm_speed=SPEED == "HIGHEST" ? 9 : 5;
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lpm_divide #(
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.LPM_WIDTHN(WIDTHN),
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.LPM_WIDTHD(WIDTHD),
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.LPM_NREPRESENTATION(NREP),
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.LPM_DREPRESENTATION(DREP),
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.LPM_PIPELINE(PIPELINE),
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.LPM_REMAINDERPOSITIVE("FALSE"), // emulate verilog % operator
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.MAXIMIZE_SPEED(lpm_speed)
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) quartus_divider (
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.clock(clock),
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.aclr(aclr),
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.clken(clken),
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.numer(numer),
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.denom(denom),
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.quotient(quotient),
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.remain(remainder)
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);
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`else
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wire [WIDTHN-1:0] numer_pipe_end;
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wire [WIDTHD-1:0] denom_pipe_end;
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if (PIPELINE == 0) begin
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assign numer_pipe_end = numer;
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assign denom_pipe_end = denom;
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end else begin
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reg [WIDTHN-1:0] numer_pipe [0:PIPELINE-1];
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reg [WIDTHD-1:0] denom_pipe [0:PIPELINE-1];
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genvar i;
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for (i = 0; i < PIPELINE-1; i++) begin : pipe_stages
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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numer_pipe[i+1] <= 0;
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denom_pipe[i+1] <= 0;
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end
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else if (clken) begin
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numer_pipe[i+1] <= numer_pipe[i];
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denom_pipe[i+1] <= denom_pipe[i];
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end
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end
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end
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always @(posedge clock or posedge aclr) begin
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if (aclr) begin
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numer_pipe[0] <= 0;
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denom_pipe[0] <= 0;
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end
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else if (clken) begin
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numer_pipe[0] <= numer;
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denom_pipe[0] <= denom;
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end
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end
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assign numer_pipe_end = numer_pipe[PIPELINE-1];
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assign denom_pipe_end = denom_pipe[PIPELINE-1];
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end
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/* * * * * * * * * * * * * * * * * * * * * * */
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/* Do the actual fallback computation here */
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/* * * * * * * * * * * * * * * * * * * * * * */
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if (NREP == "SIGNED") begin
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always @(*) begin
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if (denom_pipe_end == 0) begin
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quotient = 32'hffffffff;
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remainder = numer_pipe_end;
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end
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else if (denom_pipe_end == 32'hffffffff
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&& numer_pipe_end == 32'h80000000) begin
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// this edge case kills verilator in some cases by causing a division
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// overflow exception. INT_MIN / -1 (on x86)
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quotient = 0;
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remainder = 0;
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end
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else begin
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quotient = $signed(numer_pipe_end) / $signed(denom_pipe_end);
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remainder = $signed(numer_pipe_end) % $signed(denom_pipe_end);
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end
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end
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end
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else begin
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assign quotient = (denom_pipe_end == 0) ? 32'hffffffff : numer_pipe_end/denom_pipe_end;
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assign remainder = (denom_pipe_end == 0) ? numer_pipe_end : numer_pipe_end%denom_pipe_end;
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end
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`endif
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endgenerate
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endmodule : VX_divide
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