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kernels/rtl/cache/Notes
2019-10-22 06:02:08 -04:00

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Notes
8 kB L1 Data Cache | 16 kB L1 I cache (maybe)
[tag index offset_remaining_block bank wordOffset], use a blocksize of 128 bytes between memory and cache. So each bank gets 16 bytes.
total offset is b its
4 bits new offset, 2 bits block, 2 bits word offset
xxxxxxxIIIIIIIIoobbbyy
9876543210
bbbyyyyy
o = index into block offset
b = bank
y = word offset
I = index into cach
6 bits indexes (64 indeces) No ways || 16 indexes with 4 ways
Rest of the bits are tag bits
blocks / banks = 16 bytes, 8 banks. 128 bytes. 256 indexes (height). width is 16 bytes. 4 words per block (per bank). 17 bit tag
gtkwave ___.vcd
// Splitting it up
// word byte
wire[127:0][3:0] data_from_ram;
// word byte bank
wire[15:0][3:0] bank_data_n[3:0]
integer i;
for (i = 0; i < something; i+=8)
{
bank_data_n[0][i/8] = data_from_ram[i+0]
bank_data_n[1][i/8] = data_from_ram[i+1]
bank_data_n[2][i/8] = data_from_ram[i+2]
bank_data_n[3][i/8] = data_from_ram[i+3]
bank_data_n[4][i/8] = data_from_ram[i+4]
bank_data_n[5][i/8] = data_from_ram[i+5]
bank_data_n[6][i/8] = data_from_ram[i+6]
bank_data_n[7][i/8] = data_from_ram[i+7]
}
With Cache. If miss. Go to memory, grab all data, replace that data in the cache. Generate a new request, feed that into the cache (this one will hit), return that