193 lines
6.9 KiB
Verilog
193 lines
6.9 KiB
Verilog
`include "VX_define.vh"
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module VX_ibuffer #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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input wire freeze, // keep current warp
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VX_decode_if ibuf_enq_if,
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// outputs
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VX_decode_if ibuf_deq_if
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);
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localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + 1 + `NUM_REGS;
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localparam SIZE = `IBUF_SIZE;
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localparam SIZEW = $clog2(SIZE+1);
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localparam ADDRW = $clog2(SIZE);
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localparam NWARPSW = $clog2(`NUM_WARPS+1);
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`USE_FAST_BRAM reg [DATAW-1:0] entries [`NUM_WARPS-1:0][SIZE-1:0];
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reg [SIZEW-1:0] size_r [`NUM_WARPS-1:0];
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reg [ADDRW:0] rd_ptr_r [`NUM_WARPS-1:0];
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reg [ADDRW:0] wr_ptr_r [`NUM_WARPS-1:0];
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wire [`NUM_WARPS-1:0] q_full;
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wire [`NUM_WARPS-1:0][SIZEW-1:0] q_size;
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wire [DATAW-1:0] q_data_in;
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wire [`NUM_WARPS-1:0][DATAW-1:0] q_data_prev;
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reg [`NUM_WARPS-1:0][DATAW-1:0] q_data_out;
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wire enq_fire = ibuf_enq_if.valid && ibuf_enq_if.ready;
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wire deq_fire = ibuf_deq_if.valid && ibuf_deq_if.ready;
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for (genvar i = 0; i < `NUM_WARPS; ++i) begin
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wire writing = enq_fire && (i == ibuf_enq_if.wid);
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wire reading = deq_fire && (i == ibuf_deq_if.wid);
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wire [ADDRW-1:0] rd_ptr_a = rd_ptr_r[i][ADDRW-1:0];
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wire [ADDRW-1:0] wr_ptr_a = wr_ptr_r[i][ADDRW-1:0];
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always @(posedge clk) begin
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if (reset) begin
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rd_ptr_r[i] <= 0;
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wr_ptr_r[i] <= 0;
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size_r[i] <= 0;
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end else begin
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if (writing) begin
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if ((0 == size_r[i]) || ((1 == size_r[i]) && reading)) begin
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q_data_out[i] <= q_data_in;
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end else begin
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entries[i][wr_ptr_a] <= q_data_in;
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wr_ptr_r[i] <= wr_ptr_r[i] + ADDRW'(1);
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end
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if (!reading) begin
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size_r[i] <= size_r[i] + SIZEW'(1);
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end
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end
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if (reading) begin
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if (size_r[i] != 1) begin
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q_data_out[i] <= q_data_prev[i];
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rd_ptr_r[i] <= rd_ptr_r[i] + ADDRW'(1);
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end
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if (!writing) begin
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size_r[i] <= size_r[i] - SIZEW'(1);
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end
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end
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end
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end
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assign q_data_prev[i] = (wr_ptr_r != rd_ptr_r) ? entries[i][rd_ptr_a] : q_data_in;
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assign q_full[i] = (size_r[i] == SIZE);
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assign q_size[i] = size_r[i];
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end
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///////////////////////////////////////////////////////////////////////////
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reg [`NUM_WARPS-1:0] valid_table, valid_table_n;
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reg [`NUM_WARPS-1:0] schedule_table, schedule_table_n;
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reg [NWARPSW-1:0] num_warps;
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reg [`NW_BITS-1:0] deq_wid, deq_wid_n;
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reg deq_valid, deq_valid_n;
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reg [DATAW-1:0] deq_instr, deq_instr_n;
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always @(*) begin
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valid_table_n = valid_table;
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if (deq_fire) begin
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valid_table_n[ibuf_deq_if.wid] = (q_size[ibuf_deq_if.wid] != 1);
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end
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if (enq_fire) begin
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valid_table_n[ibuf_enq_if.wid] = 1;
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end
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end
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always @(*) begin
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deq_wid_n = 0;
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deq_valid_n = 0;
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deq_instr_n = 'x;
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schedule_table_n = schedule_table;
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if (deq_fire) begin
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schedule_table_n[ibuf_deq_if.wid] = (q_size[ibuf_deq_if.wid] != 1);
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end
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for (integer i = 0; i < `NUM_WARPS; i++) begin
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if (schedule_table_n[i]) begin
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deq_wid_n = `NW_BITS'(i);
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deq_valid_n = 1;
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deq_instr_n = (deq_fire && (ibuf_deq_if.wid == `NW_BITS'(i))) ? q_data_prev[i] : q_data_out[i];
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schedule_table_n[i] = 0;
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break;
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end
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end
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end
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wire warp_added = enq_fire && (0 == q_size[ibuf_enq_if.wid]) && (!deq_fire || ibuf_enq_if.wid != ibuf_deq_if.wid);
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wire warp_removed = deq_fire && (1 == q_size[ibuf_deq_if.wid]) && (!enq_fire || ibuf_enq_if.wid != ibuf_deq_if.wid);
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always @(posedge clk) begin
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if (reset) begin
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valid_table <= 0;
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schedule_table <= 0;
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deq_valid <= 0;
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num_warps <= 0;
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end else begin
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valid_table <= valid_table_n;
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schedule_table <= (| schedule_table_n) ? schedule_table_n : valid_table_n;
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if (enq_fire && (0 == num_warps)) begin
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deq_valid <= 1;
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deq_wid <= ibuf_enq_if.wid;
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deq_instr <= q_data_in;
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end else if (!freeze) begin
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deq_valid <= deq_valid_n;
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deq_wid <= deq_wid_n;
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deq_instr <= deq_instr_n;
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end
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if (warp_added && !warp_removed) begin
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num_warps <= num_warps + NWARPSW'(1);
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end else if (warp_removed && !warp_added) begin
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num_warps <= num_warps - NWARPSW'(1);
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end
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`ifdef VERILATOR
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begin // verify 'num_warps'
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integer nw = 0;
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for (integer i = 0; i < `NUM_WARPS; i++) begin
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nw += 32'(q_size[i] != 0);
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end
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assert(nw == 32'(num_warps));
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assert(~deq_fire || num_warps != 0);
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end
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`endif
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end
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end
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assign ibuf_enq_if.ready = ~q_full[ibuf_enq_if.wid];
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assign q_data_in = {ibuf_enq_if.thread_mask,
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ibuf_enq_if.curr_PC,
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ibuf_enq_if.ex_type,
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ibuf_enq_if.op_type,
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ibuf_enq_if.op_mod,
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ibuf_enq_if.wb,
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ibuf_enq_if.rd,
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ibuf_enq_if.rs1,
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ibuf_enq_if.rs2,
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ibuf_enq_if.rs3,
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ibuf_enq_if.imm,
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ibuf_enq_if.rs1_is_PC,
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ibuf_enq_if.rs2_is_imm,
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ibuf_enq_if.use_rs3,
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ibuf_enq_if.used_regs};
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assign ibuf_deq_if.valid = deq_valid;
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assign ibuf_deq_if.wid = deq_wid;
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assign {ibuf_deq_if.thread_mask,
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ibuf_deq_if.curr_PC,
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ibuf_deq_if.ex_type,
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ibuf_deq_if.op_type,
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ibuf_deq_if.op_mod,
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ibuf_deq_if.wb,
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ibuf_deq_if.rd,
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ibuf_deq_if.rs1,
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ibuf_deq_if.rs2,
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ibuf_deq_if.rs3,
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ibuf_deq_if.imm,
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ibuf_deq_if.rs1_is_PC,
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ibuf_deq_if.rs2_is_imm,
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ibuf_deq_if.use_rs3,
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ibuf_deq_if.used_regs} = deq_instr;
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endmodule |