d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
44 lines
1.3 KiB
Systemverilog
44 lines
1.3 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_reset_relay #(
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parameter N = 1,
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parameter MAX_FANOUT = 0
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) (
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input wire clk,
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input wire reset,
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output wire [N-1:0] reset_o
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);
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if (MAX_FANOUT >= 0 && N > (MAX_FANOUT + MAX_FANOUT/2)) begin
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localparam F = `UP(MAX_FANOUT);
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localparam R = N / F;
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`PRESERVE_NET reg [R-1:0] reset_r;
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for (genvar i = 0; i < R; ++i) begin
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always @(posedge clk) begin
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reset_r[i] <= reset;
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end
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end
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for (genvar i = 0; i < N; ++i) begin
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assign reset_o[i] = reset_r[i / F];
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end
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end else begin
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`UNUSED_VAR (clk)
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assign reset_o = {N{reset}};
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end
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endmodule
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`TRACING_ON
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