77 lines
3.1 KiB
Verilog
77 lines
3.1 KiB
Verilog
`include "VX_define.vh"
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module VX_dram_arb #(
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parameter NUM_REQUESTS = 1,
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parameter DRAM_LINE_SIZE = 1,
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parameter CORE_TAG_WIDTH = 1,
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parameter DRAM_TAG_WIDTH = 1,
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parameter DRAM_LINE_WIDTH = DRAM_LINE_SIZE * 8,
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parameter DRAM_ADDR_WIDTH = 32 - `CLOG2(DRAM_LINE_SIZE)
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) (
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input wire clk,
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input wire reset,
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// Core request
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input wire [NUM_REQUESTS-1:0] in_dram_req_valid,
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input wire [NUM_REQUESTS-1:0] in_dram_req_rw,
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input wire [NUM_REQUESTS-1:0][DRAM_LINE_SIZE-1:0] in_dram_req_byteen,
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input wire [NUM_REQUESTS-1:0][DRAM_ADDR_WIDTH-1:0] in_dram_req_addr,
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input wire [NUM_REQUESTS-1:0][DRAM_LINE_WIDTH-1:0] in_dram_req_data,
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input wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] in_dram_req_tag,
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output wire [NUM_REQUESTS-1:0] in_dram_req_ready,
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// Core response
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output wire [NUM_REQUESTS-1:0] in_dram_rsp_valid,
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output wire [NUM_REQUESTS-1:0][DRAM_LINE_WIDTH-1:0] in_dram_rsp_data,
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output wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] in_dram_rsp_tag,
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input wire [NUM_REQUESTS-1:0] in_dram_rsp_ready,
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// DRAM request
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output wire out_dram_req_valid,
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output wire out_dram_req_rw,
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output wire [DRAM_LINE_SIZE-1:0] out_dram_req_byteen,
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output wire [DRAM_ADDR_WIDTH-1:0] out_dram_req_addr,
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output wire [DRAM_LINE_WIDTH-1:0] out_dram_req_data,
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output wire [DRAM_TAG_WIDTH-1:0] out_dram_req_tag,
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input wire out_dram_req_ready,
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// DRAM response
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input wire out_dram_rsp_valid,
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input wire [DRAM_LINE_WIDTH-1:0] out_dram_rsp_data,
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input wire [DRAM_TAG_WIDTH-1:0] out_dram_rsp_tag,
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output wire out_dram_rsp_ready
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);
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reg [`REQS_BITS-1:0] bus_req_sel;
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always @(posedge clk) begin
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if (reset) begin
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bus_req_sel <= 0;
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end else begin
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bus_req_sel <= bus_req_sel + 1;
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end
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end
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assign out_dram_req_valid = in_dram_req_valid [bus_req_sel];
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assign out_dram_req_rw = in_dram_req_rw [bus_req_sel];
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assign out_dram_req_byteen= in_dram_req_byteen [bus_req_sel];
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assign out_dram_req_addr = in_dram_req_addr [bus_req_sel];
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assign out_dram_req_data = in_dram_req_data [bus_req_sel];
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assign out_dram_req_tag = {in_dram_req_tag [bus_req_sel], (`REQS_BITS)'(bus_req_sel)};
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genvar i;
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for (i = 0; i < NUM_REQUESTS; i++) begin
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assign in_dram_req_ready[i] = out_dram_req_ready && (bus_req_sel == `REQS_BITS'(i));
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end
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wire [`REQS_BITS-1:0] bus_rsp_sel = out_dram_rsp_tag[`REQS_BITS-1:0];
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for (i = 0; i < NUM_REQUESTS; i++) begin
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assign in_dram_rsp_valid[i] = out_dram_rsp_valid && (bus_rsp_sel == `REQS_BITS'(i));
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assign in_dram_rsp_data[i] = out_dram_rsp_data;
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assign in_dram_rsp_tag[i] = out_dram_rsp_tag[`REQS_BITS +: CORE_TAG_WIDTH];
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end
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assign out_dram_rsp_ready = in_dram_rsp_ready[bus_rsp_sel];
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endmodule |