d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
61 lines
1.6 KiB
C++
61 lines
1.6 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "pipeline.h"
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#include <queue>
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namespace vortex {
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class Operand : public SimObject<Operand> {
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public:
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SimPort<pipeline_trace_t*> Input;
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SimPort<pipeline_trace_t*> Output;
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Operand(const SimContext& ctx)
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: SimObject<Operand>(ctx, "Operand")
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, Input(this)
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, Output(this)
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{}
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virtual ~Operand() {}
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virtual void reset() {}
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virtual void tick() {
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if (Input.empty())
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return;
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auto trace = Input.front();
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int delay = 1;
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for (int i = 0; i < MAX_NUM_REGS; ++i) {
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bool is_iregs = trace->used_iregs.test(i);
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bool is_fregs = trace->used_fregs.test(i);
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bool is_vregs = trace->used_vregs.test(i);
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if (is_iregs || is_fregs || is_vregs) {
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if (is_iregs && i == 0)
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continue;
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++delay;
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}
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}
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Output.send(trace, delay);
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DT(3, "pipeline-operands: " << *trace);
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Input.pop();
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};
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};
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} |