41 lines
726 B
Verilog
41 lines
726 B
Verilog
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module VX_register_file (
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input wire clk,
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input wire in_write_register,
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input wire[4:0] in_rd,
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input wire[31:0] in_data,
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input wire[4:0] in_src1,
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input wire[4:0] in_src2,
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output wire[31:0] out_src1_data,
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output wire[31:0] out_src2_data
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);
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reg[31:0] registers[31:0];
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wire[31:0] write_data;
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wire[4:0] write_register;
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wire write_enable;
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assign write_data = in_data;
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assign write_register = in_rd;
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assign write_enable = in_write_register && (in_rd != 5'h0);
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always @(posedge clk) begin
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if(write_enable) begin
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registers[write_register] <= write_data;
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end
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end
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assign out_src1_data = registers[in_src1];
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assign out_src2_data = registers[in_src2];
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endmodule
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