107 lines
3.9 KiB
Verilog
107 lines
3.9 KiB
Verilog
`include "VX_define.vh"
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module VX_alu_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Inputs
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VX_alu_req_if alu_req_if,
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// Outputs
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VX_branch_ctl_if branch_ctl_if,
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VX_exu_to_cmt_if alu_commit_if
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);
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reg [`NUM_THREADS-1:0][31:0] alu_result;
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wire [`NUM_THREADS-1:0][32:0] sub_result;
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wire [`NUM_THREADS-1:0][32:0] shift_result;
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wire [`ALU_BITS-1:0] alu_op = alu_req_if.alu_op;
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wire [`NUM_THREADS-1:0][31:0] alu_in1 = alu_req_if.rs1_data;
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wire [`NUM_THREADS-1:0][31:0] alu_in2 = alu_req_if.rs2_data;
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genvar i;
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for (i = 0; i < `NUM_THREADS; i++) begin
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wire [32:0] sub_in1 = {(alu_op != `ALU_SLTU) & (alu_op != `ALU_BLTU) & (alu_op != `ALU_BGEU) & alu_in1[i][31], alu_in1[i]};
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wire [32:0] sub_in2 = {(alu_op != `ALU_SLTU) & (alu_op != `ALU_BLTU) & (alu_op != `ALU_BGEU) & alu_in2[i][31], alu_in2[i]};
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assign sub_result[i] = $signed(sub_in1) - $signed(sub_in2);
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wire [32:0] shift_in1 = {(alu_op == `ALU_SRA) & alu_in1[i][31], alu_in1[i]};
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assign shift_result[i] = $signed(shift_in1) >>> alu_in2[i][4:0];
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always @(*) begin
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case (alu_op)
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`ALU_SUB: alu_result[i] = sub_result[i][31:0];
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`ALU_SLL: alu_result[i] = alu_in1[i] << alu_in2[i][4:0];
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`ALU_SLT,
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`ALU_SLTU: alu_result[i] = 32'(sub_result[i][32]);
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`ALU_XOR: alu_result[i] = alu_in1[i] ^ alu_in2[i];
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`ALU_SRL,
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`ALU_SRA: alu_result[i] = shift_result[i][31:0];
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`ALU_OR: alu_result[i] = alu_in1[i] | alu_in2[i];
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`ALU_AND: alu_result[i] = alu_in1[i] & alu_in2[i];
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default: alu_result[i] = alu_in1[i] + alu_in2[i]; // ADD, LUI, AUIPC
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endcase
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end
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end
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wire [`NT_BITS-1:0] br_result_index;
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VX_priority_encoder #(
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.N(`NUM_THREADS)
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) choose_alu_result (
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.data_in (alu_req_if.thread_mask),
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.data_out (br_result_index),
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`UNUSED_PIN (valid_out)
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);
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wire [32:0] br_result = sub_result[br_result_index];
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wire br_sign = br_result[32];
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wire br_nzero = (| br_result[31:0]);
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wire br_sign_s1;
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wire br_nzero_s1;
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wire [`BR_BITS-1:0] br_op = `IS_BR_OP(alu_req_if.alu_op) ? `BR_OP(alu_req_if.alu_op) : `BR_NO;
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wire [`BR_BITS-1:0] br_op_s1;
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wire [31:0] br_addr = (br_op == `BR_JALR) ? alu_req_if.rs1_data[br_result_index] : alu_req_if.curr_PC;
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wire [31:0] br_dest = $signed(br_addr) + $signed(alu_req_if.offset);
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wire is_jal = (alu_op == `ALU_JAL || alu_op == `ALU_JALR);
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wire [`NUM_THREADS-1:0][31:0] alu_jal_result = is_jal ? {`NUM_THREADS{alu_req_if.next_PC}} : alu_result;
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wire stall = ~alu_commit_if.ready && alu_commit_if.valid;
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VX_generic_register #(
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.N(1 + `NW_BITS + `ISTAG_BITS + (`NUM_THREADS * 32) + `BR_BITS + 32 + 1 + 1)
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) alu_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (0),
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.in ({alu_req_if.valid, alu_req_if.warp_num, alu_req_if.issue_tag, alu_jal_result, br_op, br_dest, br_sign, br_nzero}),
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.out ({alu_commit_if.valid, branch_ctl_if.warp_num, alu_commit_if.issue_tag, alu_commit_if.data, br_op_s1, branch_ctl_if.dest, br_sign_s1, br_nzero_s1})
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);
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reg br_taken;
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always @(*) begin
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case (br_op_s1)
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`BR_NE: br_taken = br_nzero_s1;
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`BR_EQ: br_taken = ~br_nzero_s1;
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`BR_LT,
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`BR_LTU: br_taken = br_sign_s1;
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`BR_GE,
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`BR_GEU: br_taken = ~br_sign_s1;
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default: br_taken = 1'b1;
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endcase
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end
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assign branch_ctl_if.valid = alu_commit_if.valid && (br_op_s1 != `BR_NO);
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assign branch_ctl_if.taken = br_taken;
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assign alu_req_if.ready = ~stall;
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endmodule |