c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
182 lines
6.1 KiB
Systemverilog
182 lines
6.1 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_csr_unit import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0,
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parameter NUM_LANES = 1
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) (
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input wire clk,
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input wire reset,
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input base_dcrs_t base_dcrs,
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`ifdef PERF_ENABLE
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VX_mem_perf_if.slave mem_perf_if,
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VX_pipeline_perf_if.slave pipeline_perf_if,
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VX_sfu_perf_if.slave sfu_perf_if,
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`endif
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`ifdef EXT_F_ENABLE
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VX_fpu_to_csr_if.slave fpu_to_csr_if [`NUM_FPU_BLOCKS],
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`endif
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VX_commit_csr_if.slave commit_csr_if,
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VX_sched_csr_if.slave sched_csr_if,
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VX_execute_if.slave execute_if,
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VX_commit_if.master commit_if
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);
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`UNUSED_PARAM (CORE_ID)
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localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES);
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localparam PID_WIDTH = `UP(PID_BITS);
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localparam DATAW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `XLEN + `NR_BITS + 1 + NUM_LANES * 32 + PID_WIDTH + 1 + 1;
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`UNUSED_VAR (execute_if.data.rs3_data)
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reg [NUM_LANES-1:0][31:0] csr_read_data;
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reg [31:0] csr_write_data;
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wire [31:0] csr_read_data_ro, csr_read_data_rw;
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wire [31:0] csr_req_data;
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reg csr_rd_enable;
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wire csr_wr_enable;
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wire csr_req_ready;
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// wait for all pending instructions to complete
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assign sched_csr_if.alm_empty_wid = execute_if.data.wid;
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wire no_pending_instr = sched_csr_if.alm_empty;
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wire csr_req_valid = execute_if.valid && no_pending_instr;
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assign execute_if.ready = csr_req_ready && no_pending_instr;
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wire [`VX_CSR_ADDR_BITS-1:0] csr_addr = execute_if.data.imm[`VX_CSR_ADDR_BITS-1:0];
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wire [`NRI_BITS-1:0] csr_imm = execute_if.data.imm[`VX_CSR_ADDR_BITS +: `NRI_BITS];
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wire [NUM_LANES-1:0][31:0] rs1_data;
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`UNUSED_VAR (rs1_data)
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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assign rs1_data[i] = execute_if.data.rs1_data[i][31:0];
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end
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wire csr_write_enable = (execute_if.data.op_type == `INST_SFU_CSRRW);
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VX_csr_data #(
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.CORE_ID (CORE_ID)
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) csr_data (
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.clk (clk),
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.reset (reset),
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.base_dcrs (base_dcrs),
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`ifdef PERF_ENABLE
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.mem_perf_if (mem_perf_if),
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.pipeline_perf_if(pipeline_perf_if),
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.sfu_perf_if (sfu_perf_if),
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`endif
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.commit_csr_if (commit_csr_if),
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.cycles (sched_csr_if.cycles),
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.active_warps (sched_csr_if.active_warps),
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.thread_masks (sched_csr_if.thread_masks),
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`ifdef EXT_F_ENABLE
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.fpu_to_csr_if (fpu_to_csr_if),
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`endif
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.read_enable (csr_req_valid && csr_rd_enable),
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.read_uuid (execute_if.data.uuid),
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.read_wid (execute_if.data.wid),
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.read_addr (csr_addr),
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.read_data_ro (csr_read_data_ro),
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.read_data_rw (csr_read_data_rw),
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.write_enable (csr_req_valid && csr_wr_enable),
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.write_uuid (execute_if.data.uuid),
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.write_wid (execute_if.data.wid),
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.write_addr (csr_addr),
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.write_data (csr_write_data)
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);
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// CSR read
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wire [NUM_LANES-1:0][31:0] wtid, gtid;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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if (PID_BITS != 0) begin
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assign wtid[i] = 32'(execute_if.data.pid * NUM_LANES + i);
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end else begin
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assign wtid[i] = 32'(i);
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end
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assign gtid[i] = (32'(CORE_ID) << (`NW_BITS + `NT_BITS)) + (32'(execute_if.data.wid) << `NT_BITS) + wtid[i];
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end
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always @(*) begin
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csr_rd_enable = 0;
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case (csr_addr)
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`VX_CSR_THREAD_ID : csr_read_data = wtid;
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`VX_CSR_MHARTID : csr_read_data = gtid;
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default : begin
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csr_read_data = {NUM_LANES{csr_read_data_ro | csr_read_data_rw}};
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csr_rd_enable = 1;
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end
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endcase
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end
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// CSR write
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assign csr_req_data = execute_if.data.use_imm ? 32'(csr_imm) : rs1_data[0];
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assign csr_wr_enable = (csr_write_enable || (| csr_req_data));
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always @(*) begin
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case (execute_if.data.op_type)
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`INST_SFU_CSRRW: begin
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csr_write_data = csr_req_data;
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end
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`INST_SFU_CSRRS: begin
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csr_write_data = csr_read_data_rw | csr_req_data;
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end
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//`INST_SFU_CSRRC
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default: begin
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csr_write_data = csr_read_data_rw & ~csr_req_data;
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end
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endcase
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end
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// unlock the warp
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assign sched_csr_if.unlock_warp = csr_req_valid && csr_req_ready && execute_if.data.eop;
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assign sched_csr_if.unlock_wid = execute_if.data.wid;
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// send response
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wire [NUM_LANES-1:0][31:0] csr_commit_data;
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VX_elastic_buffer #(
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.DATAW (DATAW),
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.SIZE (2)
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) rsp_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (csr_req_valid),
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.ready_in (csr_req_ready),
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.data_in ({execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, csr_read_data, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop}),
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.data_out ({commit_if.data.uuid, commit_if.data.wid, commit_if.data.tmask, commit_if.data.PC, commit_if.data.rd, commit_if.data.wb, csr_commit_data, commit_if.data.pid, commit_if.data.sop, commit_if.data.eop}),
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.valid_out (commit_if.valid),
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.ready_out (commit_if.ready)
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);
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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assign commit_if.data.data[i] = `XLEN'(csr_commit_data[i]);
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end
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endmodule
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