c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
78 lines
2.4 KiB
Systemverilog
78 lines
2.4 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_index_queue #(
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parameter DATAW = 1,
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parameter SIZE = 1
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) (
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input wire clk,
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input wire reset,
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input wire [DATAW-1:0] write_data,
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output wire [`LOG2UP(SIZE)-1:0] write_addr,
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input wire push,
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input wire pop,
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output wire full,
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output wire empty,
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input wire [`LOG2UP(SIZE)-1:0] read_addr,
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output wire [DATAW-1:0] read_data
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);
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reg [DATAW-1:0] entries [SIZE-1:0];
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reg [SIZE-1:0] valid;
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reg [`LOG2UP(SIZE):0] rd_ptr, wr_ptr;
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wire [`LOG2UP(SIZE)-1:0] rd_a, wr_a;
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wire enqueue, dequeue;
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assign rd_a = rd_ptr[`LOG2UP(SIZE)-1:0];
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assign wr_a = wr_ptr[`LOG2UP(SIZE)-1:0];
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assign empty = (wr_ptr == rd_ptr);
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assign full = (wr_a == rd_a) && (wr_ptr[`LOG2UP(SIZE)] != rd_ptr[`LOG2UP(SIZE)]);
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assign enqueue = push;
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assign dequeue = !empty && !valid[rd_a]; // auto-remove when head is invalid
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`RUNTIME_ASSERT(!push || !full, ("%t: *** invalid inputs", $time));
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always @(posedge clk) begin
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if (reset) begin
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rd_ptr <= '0;
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wr_ptr <= '0;
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valid <= '0;
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end else begin
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if (enqueue) begin
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valid[wr_a] <= 1;
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wr_ptr <= wr_ptr + 1;
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end
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if (dequeue) begin
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rd_ptr <= rd_ptr + 1;
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end
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if (pop) begin
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valid[read_addr] <= 0;
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end
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end
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if (enqueue) begin
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entries[wr_a] <= write_data;
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end
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end
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assign write_addr = wr_a;
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assign read_data = entries[read_addr];
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endmodule
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`TRACING_ON
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