c1e168fdbe
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes minor update minor update minor update minor update minor update minor update cleanup cleanup cache bindings and memory perf refactory minor update minor update hw unit tests fixes minor update minor update minor update minor update minor update minor udpate minor update minor update minor update minor update minor update minor update minor update minor updates minor updates minor update minor update minor update minor update minor update minor update minor updates minor updates minor updates minor updates minor update minor update
465 lines
21 KiB
Systemverilog
465 lines
21 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_fpu_define.vh"
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`ifdef FPU_DSP
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/// Modified port of cast module from fpnew Libray
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/// reference: https://github.com/pulp-platform/fpnew
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module VX_fpu_cvt import VX_fpu_pkg::*; #(
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parameter NUM_LANES = 1,
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parameter TAGW = 1
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) (
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input wire clk,
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input wire reset,
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output wire ready_in,
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input wire valid_in,
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input wire [NUM_LANES-1:0] lane_mask,
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input wire [TAGW-1:0] tag_in,
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input wire [`INST_FRM_BITS-1:0] frm,
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input wire is_itof,
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input wire is_signed,
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input wire [NUM_LANES-1:0][31:0] dataa,
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output wire [NUM_LANES-1:0][31:0] result,
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output wire has_fflags,
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output wire [`FP_FLAGS_BITS-1:0] fflags,
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output wire [TAGW-1:0] tag_out,
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input wire ready_out,
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output wire valid_out
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);
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// Constants
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localparam MAN_BITS = 23;
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localparam EXP_BITS = 8;
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localparam EXP_BIAS = 2**(EXP_BITS-1)-1;
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localparam logic [EXP_BITS-1:0] QNAN_EXPONENT = 2**EXP_BITS-1;
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localparam logic [MAN_BITS-1:0] QNAN_MANTISSA = 2**(MAN_BITS-1);
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// Use 32-bit integer
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localparam MAX_INT_WIDTH = 32;
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// The internal mantissa includes normal bit or an entire integer
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localparam INT_MAN_WIDTH = `MAX(MAN_BITS + 1, MAX_INT_WIDTH);
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// The lower 2p+3 bits of the internal FMA result will be needed for leading-zero detection
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localparam LZC_RESULT_WIDTH = `CLOG2(INT_MAN_WIDTH);
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// The internal exponent must be able to represent the smallest denormal input value as signed
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// or the number of bits in an integer
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localparam INT_EXP_WIDTH = `MAX(`CLOG2(MAX_INT_WIDTH), `MAX(EXP_BITS, `CLOG2(EXP_BIAS + MAN_BITS))) + 1;
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// shift amount for denormalization
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localparam SHAMT_BITS = `CLOG2(INT_MAN_WIDTH+1);
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localparam FMT_SHIFT_COMPENSATION = INT_MAN_WIDTH - 1 - MAN_BITS;
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localparam NUM_FP_STICKY = 2 * INT_MAN_WIDTH - MAN_BITS - 1; // removed mantissa, 1. and R
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localparam NUM_INT_STICKY = 2 * INT_MAN_WIDTH - MAX_INT_WIDTH; // removed int and R
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// Input processing
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fclass_t [NUM_LANES-1:0] fclass;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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VX_fpu_class #(
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.EXP_BITS (EXP_BITS),
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.MAN_BITS (MAN_BITS)
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) fp_class (
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.exp_i (dataa[i][30:23]),
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.man_i (dataa[i][22:0]),
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.clss_o (fclass[i])
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);
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end
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wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] input_mant;
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wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] input_exp;
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wire [NUM_LANES-1:0] input_sign;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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wire [INT_MAN_WIDTH-1:0] int_mantissa;
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wire [INT_MAN_WIDTH-1:0] fmt_mantissa;
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wire fmt_sign = dataa[i][31];
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wire int_sign = dataa[i][31] && is_signed;
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assign int_mantissa = int_sign ? (-dataa[i]) : dataa[i];
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assign fmt_mantissa = INT_MAN_WIDTH'({fclass[i].is_normal, dataa[i][MAN_BITS-1:0]});
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assign input_exp[i] = {1'b0, dataa[i][MAN_BITS +: EXP_BITS]} + INT_EXP_WIDTH'({1'b0, fclass[i].is_subnormal});
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assign input_mant[i] = is_itof ? int_mantissa : fmt_mantissa;
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assign input_sign[i] = is_itof ? int_sign : fmt_sign;
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end
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// Pipeline stage0
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wire valid_in_s0;
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wire [NUM_LANES-1:0] lane_mask_s0;
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wire [TAGW-1:0] tag_in_s0;
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wire is_itof_s0;
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wire unsigned_s0;
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wire [2:0] rnd_mode_s0;
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fclass_t [NUM_LANES-1:0] fclass_s0;
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wire [NUM_LANES-1:0] input_sign_s0;
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wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] fmt_exponent_s0;
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wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] encoded_mant_s0;
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wire stall;
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VX_pipe_register #(
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.DATAW (1 + NUM_LANES + TAGW + 1 + `INST_FRM_BITS + 1 + NUM_LANES * ($bits(fclass_t) + 1 + INT_EXP_WIDTH + INT_MAN_WIDTH)),
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.RESETW (1)
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) pipe_reg0 (
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.clk (clk),
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.reset (reset),
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.enable (~stall),
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.data_in ({valid_in, lane_mask, tag_in, is_itof, !is_signed, frm, fclass, input_sign, input_exp, input_mant}),
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.data_out ({valid_in_s0, lane_mask_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, fclass_s0, input_sign_s0, fmt_exponent_s0, encoded_mant_s0})
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);
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// Normalization
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wire [NUM_LANES-1:0][LZC_RESULT_WIDTH-1:0] renorm_shamt_s0; // renormalization shift amount
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wire [NUM_LANES-1:0] mant_is_zero_s0; // for integer zeroes
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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wire mant_is_nonzero_s0;
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VX_lzc #(
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.N (INT_MAN_WIDTH)
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) lzc (
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.data_in (encoded_mant_s0[i]),
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.data_out (renorm_shamt_s0[i]),
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.valid_out (mant_is_nonzero_s0)
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);
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assign mant_is_zero_s0[i] = ~mant_is_nonzero_s0;
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end
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wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] input_mant_n_s0; // normalized input mantissa
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wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_n_s0; // unbiased true exponent
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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// Realign input mantissa, append zeroes if destination is wider
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assign input_mant_n_s0[i] = encoded_mant_s0[i] << renorm_shamt_s0[i];
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// Unbias exponent and compensate for shift
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wire [INT_EXP_WIDTH-1:0] fp_input_exp_s0 = fmt_exponent_s0[i] + INT_EXP_WIDTH'(FMT_SHIFT_COMPENSATION - EXP_BIAS) - INT_EXP_WIDTH'({1'b0, renorm_shamt_s0[i]});
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wire [INT_EXP_WIDTH-1:0] int_input_exp_s0 = INT_EXP_WIDTH'(INT_MAN_WIDTH-1) - INT_EXP_WIDTH'({1'b0, renorm_shamt_s0[i]});
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assign input_exp_n_s0[i] = is_itof_s0 ? int_input_exp_s0 : fp_input_exp_s0;
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end
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// Pipeline stage1
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wire valid_in_s1;
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wire [NUM_LANES-1:0] lane_mask_s1;
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wire [TAGW-1:0] tag_in_s1;
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wire is_itof_s1;
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wire unsigned_s1;
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wire [2:0] rnd_mode_s1;
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fclass_t [NUM_LANES-1:0] fclass_s1;
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wire [NUM_LANES-1:0] input_sign_s1;
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wire [NUM_LANES-1:0] mant_is_zero_s1;
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wire [NUM_LANES-1:0][INT_MAN_WIDTH-1:0] input_mant_s1;
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wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] input_exp_s1;
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VX_pipe_register #(
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.DATAW (1 + NUM_LANES + TAGW + 1 + `INST_FRM_BITS + 1 + NUM_LANES * ($bits(fclass_t) + 1 + 1 + INT_MAN_WIDTH + INT_EXP_WIDTH)),
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.RESETW (1)
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) pipe_reg1 (
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.clk (clk),
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.reset (reset),
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.enable (~stall),
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.data_in ({valid_in_s0, lane_mask_s0, tag_in_s0, is_itof_s0, unsigned_s0, rnd_mode_s0, fclass_s0, input_sign_s0, mant_is_zero_s0, input_mant_n_s0, input_exp_n_s0}),
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.data_out ({valid_in_s1, lane_mask_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, fclass_s1, input_sign_s1, mant_is_zero_s1, input_mant_s1, input_exp_s1})
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);
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// Perform adjustments to mantissa and exponent
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wire [NUM_LANES-1:0][2*INT_MAN_WIDTH:0] destination_mant_s1;
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wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s1;
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wire [NUM_LANES-1:0] of_before_round_s1;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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reg [2*INT_MAN_WIDTH:0] preshift_mant_s1; // mantissa before final shift
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reg [SHAMT_BITS-1:0] denorm_shamt_s1; // shift amount for denormalization
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reg [INT_EXP_WIDTH-1:0] final_exp_tmp_s1; // after eventual adjustments
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reg of_before_round_tmp_s1;
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always @(*) begin
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final_exp_tmp_s1 = input_exp_s1[i] + INT_EXP_WIDTH'(EXP_BIAS); // take exponent as is, only look at lower bits
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preshift_mant_s1 = {input_mant_s1[i], 33'b0};
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denorm_shamt_s1 = '0;
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of_before_round_tmp_s1 = 1'b0;
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if (is_itof_s1) begin
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if ($signed(input_exp_s1[i]) >= INT_EXP_WIDTH'($signed(2**EXP_BITS-1-EXP_BIAS))) begin
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// Overflow or infinities (for proper rounding)
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final_exp_tmp_s1 = (2**EXP_BITS-2); // largest normal value
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preshift_mant_s1 = ~0; // largest normal value and RS bits set
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of_before_round_tmp_s1 = 1'b1;
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end else if ($signed(input_exp_s1[i]) < INT_EXP_WIDTH'($signed(-MAN_BITS-EXP_BIAS))) begin
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// Limit the shift to retain sticky bits
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final_exp_tmp_s1 = '0; // denormal result
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denorm_shamt_s1 = (2 + MAN_BITS); // to sticky
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end else if ($signed(input_exp_s1[i]) < INT_EXP_WIDTH'($signed(1-EXP_BIAS))) begin
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// Denormalize underflowing values
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final_exp_tmp_s1 = '0; // denormal result
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denorm_shamt_s1 = SHAMT_BITS'(1-EXP_BIAS) - SHAMT_BITS'(input_exp_s1[i]); // adjust right shifting
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end
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end else begin
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if ($signed(input_exp_s1[i]) >= $signed(INT_EXP_WIDTH'(MAX_INT_WIDTH-1) + INT_EXP_WIDTH'(unsigned_s1))) begin
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// overflow: when converting to unsigned the range is larger by one
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of_before_round_tmp_s1 = 1'b1;
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end else if ($signed(input_exp_s1[i]) < INT_EXP_WIDTH'($signed(-1))) begin
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// underflow
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denorm_shamt_s1 = MAX_INT_WIDTH+1; // all bits go to the sticky
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end else begin
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// By default right shift mantissa to be an integer
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denorm_shamt_s1 = SHAMT_BITS'(MAX_INT_WIDTH-1) - SHAMT_BITS'(input_exp_s1[i]);
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end
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end
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end
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assign destination_mant_s1[i] = preshift_mant_s1 >> denorm_shamt_s1;
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assign final_exp_s1[i] = final_exp_tmp_s1;
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assign of_before_round_s1[i] = of_before_round_tmp_s1;
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end
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// Pipeline stage2
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wire valid_in_s2;
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wire [NUM_LANES-1:0] lane_mask_s2;
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wire [TAGW-1:0] tag_in_s2;
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wire is_itof_s2;
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wire unsigned_s2;
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wire [2:0] rnd_mode_s2;
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fclass_t [NUM_LANES-1:0] fclass_s2;
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wire [NUM_LANES-1:0] mant_is_zero_s2;
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wire [NUM_LANES-1:0] input_sign_s2;
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wire [NUM_LANES-1:0][2*INT_MAN_WIDTH:0] destination_mant_s2;
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wire [NUM_LANES-1:0][INT_EXP_WIDTH-1:0] final_exp_s2;
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wire [NUM_LANES-1:0] of_before_round_s2;
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VX_pipe_register #(
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.DATAW (1 + NUM_LANES + TAGW + 1 + 1 + `INST_FRM_BITS + NUM_LANES * ($bits(fclass_t) + 1 + 1 + (2*INT_MAN_WIDTH+1) + INT_EXP_WIDTH + 1)),
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.RESETW (1)
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) pipe_reg2 (
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.clk (clk),
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.reset (reset),
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.enable (~stall),
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.data_in ({valid_in_s1, lane_mask_s1, tag_in_s1, is_itof_s1, unsigned_s1, rnd_mode_s1, fclass_s1, mant_is_zero_s1, input_sign_s1, destination_mant_s1, final_exp_s1, of_before_round_s1}),
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.data_out ({valid_in_s2, lane_mask_s2, tag_in_s2, is_itof_s2, unsigned_s2, rnd_mode_s2, fclass_s2, mant_is_zero_s2, input_sign_s2, destination_mant_s2, final_exp_s2, of_before_round_s2})
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);
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wire [NUM_LANES-1:0] rounded_sign_s2;
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wire [NUM_LANES-1:0][31:0] rounded_abs_s2; // absolute value of result after rounding
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wire [NUM_LANES-1:0] int_round_has_sticky_s2;
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wire [NUM_LANES-1:0] fp_round_has_sticky_s2;
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// Rouding and classification
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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wire [MAN_BITS-1:0] final_mant_s2; // mantissa after adjustments
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wire [MAX_INT_WIDTH-1:0] final_int_s2; // integer shifted in position
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wire [1:0] round_sticky_bits_s2;
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wire [31:0] fmt_pre_round_abs_s2;
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wire [31:0] pre_round_abs_s2;
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wire [1:0] int_round_sticky_bits_s2, fp_round_sticky_bits_s2;
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// Extract final mantissa and round bit, discard the normal bit (for FP)
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assign {final_mant_s2, fp_round_sticky_bits_s2[1]} = destination_mant_s2[i][2*INT_MAN_WIDTH-1 : 2*INT_MAN_WIDTH-1 - (MAN_BITS+1) + 1];
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assign {final_int_s2, int_round_sticky_bits_s2[1]} = destination_mant_s2[i][2*INT_MAN_WIDTH : 2*INT_MAN_WIDTH - (MAX_INT_WIDTH+1) + 1];
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// Collapse sticky bits
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assign fp_round_sticky_bits_s2[0] = (| destination_mant_s2[i][NUM_FP_STICKY-1:0]);
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assign int_round_sticky_bits_s2[0] = (| destination_mant_s2[i][NUM_INT_STICKY-1:0]);
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assign fp_round_has_sticky_s2[i] = (| fp_round_sticky_bits_s2);
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assign int_round_has_sticky_s2[i] = (| int_round_sticky_bits_s2);
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// select RS bits for destination operation
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assign round_sticky_bits_s2 = is_itof_s2 ? fp_round_sticky_bits_s2 : int_round_sticky_bits_s2;
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// Pack exponent and mantissa into proper rounding form
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assign fmt_pre_round_abs_s2 = {1'b0, final_exp_s2[i][EXP_BITS-1:0], final_mant_s2[MAN_BITS-1:0]};
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// Select output with destination format and operation
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assign pre_round_abs_s2 = is_itof_s2 ? fmt_pre_round_abs_s2 : final_int_s2;
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// Perform the rounding
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VX_fpu_rounding #(
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.DAT_WIDTH (32)
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) fp_rounding (
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.abs_value_i (pre_round_abs_s2),
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.sign_i (input_sign_s2[i]),
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.round_sticky_bits_i (round_sticky_bits_s2),
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.rnd_mode_i (rnd_mode_s2),
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.effective_subtraction_i (1'b0),
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.abs_rounded_o (rounded_abs_s2[i]),
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.sign_o (rounded_sign_s2[i]),
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`UNUSED_PIN (exact_zero_o)
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);
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end
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// Pipeline stage3
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wire valid_in_s3;
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wire [NUM_LANES-1:0] lane_mask_s3;
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wire [TAGW-1:0] tag_in_s3;
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wire is_itof_s3;
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wire unsigned_s3;
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fclass_t [NUM_LANES-1:0] fclass_s3;
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wire [NUM_LANES-1:0] mant_is_zero_s3;
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wire [NUM_LANES-1:0] input_sign_s3;
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wire [NUM_LANES-1:0] rounded_sign_s3;
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wire [NUM_LANES-1:0][31:0] rounded_abs_s3;
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wire [NUM_LANES-1:0] of_before_round_s3;
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wire [NUM_LANES-1:0] int_round_has_sticky_s3;
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wire [NUM_LANES-1:0] fp_round_has_sticky_s3;
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VX_pipe_register #(
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.DATAW (1 + NUM_LANES + TAGW + 1 + 1 + NUM_LANES * ($bits(fclass_t) + 1 + 1 + 32 + 1 + 1 + 1 + 1)),
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.RESETW (1)
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) pipe_reg3 (
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.clk (clk),
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.reset (reset),
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.enable (~stall),
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.data_in ({valid_in_s2, lane_mask_s2, tag_in_s2, is_itof_s2, unsigned_s2, fclass_s2, mant_is_zero_s2, input_sign_s2, rounded_abs_s2, rounded_sign_s2, of_before_round_s2, int_round_has_sticky_s2, fp_round_has_sticky_s2}),
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.data_out ({valid_in_s3, lane_mask_s3, tag_in_s3, is_itof_s3, unsigned_s3, fclass_s3, mant_is_zero_s3, input_sign_s3, rounded_abs_s3, rounded_sign_s3, of_before_round_s3, int_round_has_sticky_s3, fp_round_has_sticky_s3})
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);
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wire [NUM_LANES-1:0] of_after_round_s3;
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wire [NUM_LANES-1:0] uf_after_round_s3;
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wire [NUM_LANES-1:0][31:0] fmt_result_s3;
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wire [NUM_LANES-1:0][31:0] rounded_int_res_s3; // after possible inversion
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wire [NUM_LANES-1:0] rounded_int_res_zero_s3; // after rounding
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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// Assemble regular result, nan box short ones. Int zeroes need to be detected
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assign fmt_result_s3[i] = (is_itof_s3 & mant_is_zero_s3[i]) ? 0 : {rounded_sign_s3[i], rounded_abs_s3[i][EXP_BITS+MAN_BITS-1:0]};
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// Classification after rounding select by destination format
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assign uf_after_round_s3[i] = (rounded_abs_s3[i][EXP_BITS+MAN_BITS-1:MAN_BITS] == 0); // denormal
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assign of_after_round_s3[i] = (rounded_abs_s3[i][EXP_BITS+MAN_BITS-1:MAN_BITS] == ~0); // inf exp.
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// Negative integer result needs to be brought into two's complement
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assign rounded_int_res_s3[i] = rounded_sign_s3[i] ? (-rounded_abs_s3[i]) : rounded_abs_s3[i];
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assign rounded_int_res_zero_s3[i] = (rounded_int_res_s3[i] == 0);
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end
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// FP Special case handling
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wire [NUM_LANES-1:0][31:0] fp_special_result_s3;
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fflags_t [NUM_LANES-1:0] fp_special_status_s3;
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wire [NUM_LANES-1:0] fp_result_is_special_s3;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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// Detect special case from source format, I2F casts don't produce a special result
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assign fp_result_is_special_s3[i] = ~is_itof_s3 & (fclass_s3[i].is_zero | fclass_s3[i].is_nan);
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// Signalling input NaNs raise invalid flag, otherwise no flags set
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assign fp_special_status_s3[i] = fclass_s3[i].is_signaling ? {1'b1, 4'h0} : 5'h0; // invalid operation
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// Assemble result according to destination format
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assign fp_special_result_s3[i] = fclass_s3[i].is_zero ? (32'(input_sign_s3) << 31) // signed zero
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: {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN
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end
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// INT Special case handling
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reg [NUM_LANES-1:0][31:0] int_special_result_s3;
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fflags_t [NUM_LANES-1:0] int_special_status_s3;
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wire [NUM_LANES-1:0] int_result_is_special_s3;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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// Assemble result according to destination format
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always @(*) begin
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if (input_sign_s3[i] && !fclass_s3[i].is_nan) begin
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int_special_result_s3[i][30:0] = '0; // alone yields 2**(31)-1
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int_special_result_s3[i][31] = ~unsigned_s3; // for unsigned casts yields 2**31
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end else begin
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int_special_result_s3[i][30:0] = 2**(31) - 1; // alone yields 2**(31)-1
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int_special_result_s3[i][31] = unsigned_s3; // for unsigned casts yields 2**31
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end
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end
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// Detect special case from source format (inf, nan, overflow, nan-boxing or negative unsigned)
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|
assign int_result_is_special_s3[i] = fclass_s3[i].is_nan
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| fclass_s3[i].is_inf
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| of_before_round_s3[i]
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| (input_sign_s3[i] & unsigned_s3 & ~rounded_int_res_zero_s3[i]);
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|
|
|
// All integer special cases are invalid
|
|
assign int_special_status_s3[i] = {1'b1, 4'h0};
|
|
end
|
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|
|
// Result selection and Output handshake
|
|
|
|
fflags_t [NUM_LANES-1:0] tmp_fflags_s3;
|
|
wire [NUM_LANES-1:0][31:0] tmp_result_s3;
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|
|
|
for (genvar i = 0; i < NUM_LANES; ++i) begin
|
|
fflags_t fp_regular_status_s3, int_regular_status_s3;
|
|
fflags_t fp_status_s3, int_status_s3;
|
|
wire [31:0] fp_result_s3, int_result_s3;
|
|
|
|
wire inexact_s3 = is_itof_s3 ? fp_round_has_sticky_s3[i] // overflow is invalid in i2f;
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|
: (fp_round_has_sticky_s3[i] || (~fclass_s3[i].is_inf && (of_before_round_s3[i] || of_after_round_s3[i])));
|
|
|
|
assign fp_regular_status_s3.NV = is_itof_s3 & (of_before_round_s3[i] | of_after_round_s3[i]); // overflow is invalid for I2F casts
|
|
assign fp_regular_status_s3.DZ = 1'b0; // no divisions
|
|
assign fp_regular_status_s3.OF = ~is_itof_s3 & (~fclass_s3[i].is_inf & (of_before_round_s3[i] | of_after_round_s3[i])); // inf casts no OF
|
|
assign fp_regular_status_s3.UF = uf_after_round_s3[i] & inexact_s3;
|
|
assign fp_regular_status_s3.NX = inexact_s3;
|
|
|
|
assign int_regular_status_s3 = int_round_has_sticky_s3[i] ? {4'h0, 1'b1} : 5'h0;
|
|
|
|
assign fp_result_s3 = fp_result_is_special_s3[i] ? fp_special_result_s3[i] : fmt_result_s3[i];
|
|
assign int_result_s3 = int_result_is_special_s3[i] ? int_special_result_s3[i] : rounded_int_res_s3[i];
|
|
|
|
assign fp_status_s3 = fp_result_is_special_s3[i] ? fp_special_status_s3[i] : fp_regular_status_s3;
|
|
assign int_status_s3 = int_result_is_special_s3[i] ? int_special_status_s3[i] : int_regular_status_s3;
|
|
|
|
// Select output depending on special case detection
|
|
assign tmp_result_s3[i] = is_itof_s3 ? fp_result_s3 : int_result_s3;
|
|
assign tmp_fflags_s3[i] = is_itof_s3 ? fp_status_s3 : int_status_s3;
|
|
end
|
|
|
|
assign stall = ~ready_out && valid_out;
|
|
|
|
fflags_t fflags_merged;
|
|
`FPU_MERGE_FFLAGS(fflags_merged, tmp_fflags_s3, lane_mask_s3, NUM_LANES);
|
|
|
|
VX_pipe_register #(
|
|
.DATAW (1 + TAGW + (NUM_LANES * 32) + `FP_FLAGS_BITS),
|
|
.RESETW (1)
|
|
) pipe_reg4 (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.enable (!stall),
|
|
.data_in ({valid_in_s3, tag_in_s3, tmp_result_s3, fflags_merged}),
|
|
.data_out ({valid_out, tag_out, result, fflags})
|
|
);
|
|
|
|
assign ready_in = ~stall;
|
|
|
|
assign has_fflags = 1'b1;
|
|
|
|
endmodule
|
|
`endif
|