18 lines
534 B
Verilog
18 lines
534 B
Verilog
`include "VX_tex_define.vh"
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module VX_lerp_64 #(
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) (
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input wire [`BLEND_FRAC_64-1:0] blend,
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input wire [1:0][63:0] in_texels,
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output wire [63:0] lerp_texel
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);
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wire [63:0] lerp_i1;
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wire [63:0] lerp_i2; // >> BLEND_FRAC_64 / >> 8
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assign lerp_i1 = (in_texels[0] - in_texels[1]) * blend;
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assign lerp_i2 = in_texels[1] + {8'h00,lerp_i1[63:56], 8'h00,lerp_i1[47:40], 8'h00,lerp_i1[31:24], 8'h00,lerp_i1[15:8]};
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assign lerp_texel = lerp_i2 & 64'h00ff00ff00ff00ff;
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endmodule |